TCI6636K2H Datasheet, PDF (290/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG
registers in the PLL Controller. (See ‘‘Reset Configuration Register (RSTCFG)’’ on page 302 and 6.3.2 ‘‘CIC
Registers’’ on page 159.)
– Local reset
– NMI
– NMI followed by a time delay and then a local reset for the C66x CorePac selected
– Hard reset by requesting reset via the PLL Controller
• LPSC MMRs (memory-mapped registers)
For more details see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.4 ‘‘Related
Documentation from Texas Instruments’’ on page 19)
10.4.5 ARM CorePac Reset
The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such as the
Cortex-A15 processor, memory subsystem, debug logic, etc. The ARM CorePac incorporates the PSC to generate
resets for its internal modules. Details of reset generation and distribution inside the ARM CorePac can be found in
the KeyStone II ARM CorePac Users Guide listed in ‘‘Related Documentation from Texas Instruments’’ on page 19.
10.4.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLL Controller processes only the highest priority reset
request. The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/soft reset
10.4.7 Reset Controller Register
The reset controller registers are part of the PLL Controller MMRs. All TCI6636K2H device-specific MMRs are
covered in Section 10.5.2 ‘‘PLL Controller Memory Map’’ on page 296. For more details on these registers and how
to program them, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.4 ‘‘Related
Documentation from Texas Instruments’’ on page 19.
10.4.8 Reset Electrical Data/Timing
Table 10-10 Reset Timing Requirements ⁽¹⁾
(see Figure 10-4 and Figure 10-5)
No.
RESETFULL Pin Reset
1 tw(RESETFULL)
Pulse width - pulse width RESETFULL low
Soft/Hard-Reset
2 tw(RESET)
End of Table 10-10
Pulse width - pulse width RESET low
1 C = 1/SYSCLK1 clock frequency in ns
Min Max
500C
500C
Unit
ns
ns
290 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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