TCI6636K2H Datasheet, PDF (221/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-13
BAR cfg
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
BAR Config / PCIe Window Sizes
BAR0
PCIe MMRs
BAR1
32
16
16
32
16
16
32
32
64
4
4
4
BAR2
32
16
32
32
16
32
32
32
64
128
128
128
32-Bit Address Translation
BAR3
BAR4
32
32
32
64
32
64
32
64
64
64
64
64
64
64
64
128
128
256
128
128
128
256
256
256
64-Bit Address Translation
BAR5
BAR2/3
BAR4/5
Clone of BAR4
256
512
1024
2048
256
512
1024
2048
8.1.2.3.2 HyperLink Boot Device Configuration
Figure 8-11 HyperLink Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13
12
11 10 9
8
765
Port
RefClk
Data Rate
Reserved
Boot Master=1
Sys PLL Cfg
Port
RefClk
Data Rate
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
4321
1110
1110
0
Lendian
Lendian
Table 8-14 HyperLink Boot Device Configuration Field Descriptions (Part 1 of 2)
Bit Field
Description
16 Port
HyperLink port
0 = HyperLink0
1 = HyperLink1
15-14 Ref Clocks
HyperLink reference clock configuration
0 = 125 MHz
1 = 156.25 MHz
2-3 = Reserved
13-12 Data Rate
HyperLink data rate configuration
0 = 1.25 GBs
1 = 3.125 GBs
2 = 6.25 GBs
3 = 12.5GBs
11-9 Reserved/ARM When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the
PLL Setting [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 8-27 shows settings for various input clock
frequencies.
When Boot Master =1 (C66x is Boot Master), pin [10:9] are reserved.
8
Boot Master Boot Master select
0 = ARM is boot master (default)
1 = C66x is boot master
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Device Boot and Configuration 221