TCI6636K2H Datasheet, PDF (272/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.2.1.1 Core-Before-IO Power Sequencing
The details of the Core-before-IO power sequencing are defined in Table 10-2. Figure 10-1 shows power sequencing
and reset control of the TCI6636K2H. POR may be removed after the power has been stable for the required
100 μsec. RESETFULL must be held low for a period (see item 9 in Figure 10-1) after the rising edge of POR, but
may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on
the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active
before POR can be removed.
Note—TI recommends a maximum of 80 ms between one power rail being valid and the next power rail in
the sequence starting to ramp.
Table 10-2 Core Before IO Power Sequencing (Part 1 of 2)
Item
1
System State
Begin Power Stabilization Phase
• CVDD(core AVS) ramp up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created
from POR) is put into the reset state.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a
• CVDD1 and CVDDT1 (core constant) ramp at the same time or within 80 ms of CVDD. Although ramping CVDD1 and CVDDT1
simultaneously with CVDD is permitted, the voltage for CVDD1 and CVDDT1 must never exceed CVDD until after CVDD has reached a
valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 and CVDDT1 should trail CVDD as
this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If,
however, CVDD1 and CVDDT1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the order of
twice the specified draw of CVDD1 and CVDDT1.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• The timing for CVDD1 and CVDDT1 is based on CVDD valid. CVDD1 and CVDDT1 and DVDD18/ADDAVH/AVDDAx may be enabled at the
same time but do not need to ramp simultaneously. CVDD1 and CVDDT1 may be valid before or after DVDD18/ADDAVH/AVDDAx are
valid, as long as the timing above is met.
2b
• VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD. DVDD18 must be enabled within 80 ms of CVDD valid
and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100 ms from the time when
CVDD is valid to the time when DVDD18 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD valid. DVDD18/ADDAVH/AVDDAx and CVDD1 and CVDDT1 may be enabled
at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after CVDD1 and
CVDDT1 are valid, as long as the timing above is met.
2c
• Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or be held in a static state with one leg high and one leg low.
2d
• The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 7.
3
• DVDD15 can ramp up within 80ms of when DVDD18 is valid.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin
before DVDD18 is valid could cause damage to the device.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
• RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high.
4
• VDDALV, VDDUSB, VP and VPTX ramp up within 80ms of when DVDD15 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
• DVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSB, VP and VPTX are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6
• POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
272 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback