TCI6636K2H Datasheet, PDF (269/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
9.4 Power Supply to Peripheral I/O Mapping
Table 9-4
Power Supply to Peripheral I/O Mapping ^{(1) (2)}
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Power Supply
CVDD
Supply core AVS voltage
VDDALV
VDDAHV
DVDD15
SerDes IO voltage
1.5-V supply I/O voltage
I/O Buffer Type
Associated Peripheral
SYSCLK(P|N) PLL input buffer
ALTCORECLK(P|N) PLL input buffer
SRIOSGMIICLK(P|N) SerDes PLL input buffer
LJCB
DDR3ACLK(P|N) PLL input buffer
DDR3BCLK(P|N) PLL input buffer
PASSCLK(P|N) PLL input buffer
ARMCLK(P|N) PLL input buffer
LJCB
SERDES low voltage
PCIECLK(P|N) SerDes Clock Reference
SerDes/CML
HYP0CLK(P|N) SerDes Clock Reference
HYP1CLK(P|N) SerDes Clock Reference
USBCLK(P|M) SerDes Clock Reference
DDR3A, DDR3B (1.5 V) All DDR3A, DDR3B memory controller peripheral I/O buffer
DVDD18
1.8-V supply I/O voltage
End of Table 9-4
LVCMOS (1.8 V)
Open-drain (1.8 V)
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All TIMER peripheral I/O buffer
All SPI peripheral I/O buffer
All RESETs, NMI, control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All Hyperlink sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
All I²C peripheral I/O buffer
1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and
clock input buffers.
2 Please see the Hardware Design Guide for KeyStone II Devices (in development) for more information about individual peripheral I/O.
Copyright 2013 Texas Instruments Incorporated
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Device Operating Conditions 269