TCI6636K2H Datasheet, PDF (313/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-34 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
23
BYPASS
PLL bypass mode:
0 = PLL is not in BYPASS mode
1 = PLL is in BYPASS mode
22-19 CLKOD
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16.
CLKOD field is loaded with output divide value minus 1
18-6 PLLM
A 13-bit field that selects the values for the multiplication factor (see note below). PLLM field is loaded with the multiply
factor minus 1.
5-0 PLLD
End of Table 10-34
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
Figure 10-31 PASS PLL Control Register 1 (PASSPLLCTL1)
31
15
14
13
Reserved
PLLRST PAPLL
RW - 00000000000000000
RW-0 RW-0
Legend: RW = Read/Write; -n = value after reset
12
7
Reserved
RW-000000
6
ENSAT
RW-0
5
4
Reserved
R-00
3
0
BWADJ[11:8]
RW- 0000
Table 10-35 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
Bit
Field
Description
31-15 Reserved
Reserved
14
PLLRST
PLL Reset bit
0 = PLL Reset is released
1 = PLL Reset is asserted
13
PAPLL
12-7 Reserved
6
ENSAT
5-4 Reserved
3-0 BWADJ[11:8]
End of Table 10-35
0 = Not supported
1 = PAPLL
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
10.7.3 PASS PLL Device-Specific Information
As shown in Figure 10-29, the output of PASS PLL (PLLOUT) is divided by 3 and directly fed to the Network
Coprocessor. During power-on resets, the internal clocks of the PASS PLL are affected as described in
Section 10.4 ‘‘Reset Controller’’ on page 287. The PASS PLL is unlocked only during the power-up sequence and is
locked by the time the RESETSTAT pin goes high. It does not lose lock during any other resets.
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TCI6636K2H Peripheral Information and Electrical Specifications 313