TCI6636K2H Datasheet, PDF (30/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
4.3 ARM Cortex-A15 Processor
4.3.1 Overview
The ARM Cortex™-A15 processor incorporates the technologies available in the ARM7™ architecture. These
technologies include NEON™ for media and signal processing and Jazelle™ RCT for acceleration of real-time
compilers, Thumb®-2 technology for code density, and the VFPv4 floating point architecture. For details, see the
ARM Cortex™-A15 Processor Technical Reference Manual.
4.3.2 Features
Table 4-1 shows the features supported by the Cortex-A15 processor core.
Table 4-1
Cortex-A15 Processor Core Supported Features
Features
ARM version 7-A ISA
Cortex-A15 processor version
Integer core
NEON core
Architecture Extensions
L1 Lcache and Dcache
L2 cache
Cache Coherency
Branch target address cache
Enhanced memory management unit
Buses
Non-invasive Debug Support
Misc Debug Support
Clocking
Voltage
Power
End of Table 4-1
Description
Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and media
extensions
Backward compatible with previous ARM ISA versions
R2P4
Main core for processing integer instructions
Gives greatly enhanced throughput for media workloads and VFP-Lite support
Security, virtualization and LPAE (40-bit physical address) extensions
32KB, 2-way, 16 word line, 128 bit interface
4096KB, 16-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported shared between cores
L2 valid bits cleared by software loop or by hardware
Support for coherent memory accesses between A15 cores and other non-core master peripherals (Ex: EDMA)
in the DDR3A and MSMC SRAM space.
Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return stack,
and an indirect predictor
Mapping sizes are 4KB, 64KB, 1MB, and 16MB
128b AXI4 internal bus from Cortex-A15 converted to a 256b VBUSM to interface (through the MSMC) with
MSMC SRAM, DDR EMIF, ROM, Interrupt controller and other system peripherals
Processor instruction trace using 4x Program Trace Macrocell (Coresight™ PTM), Data trace (print-f style
debug) using System Trace Macrocell (Coresight™ STM) and Performance Monitoring Units (PMU)
JTAG based debug and Cross triggering
Dedicated ARM PLL for flexible clocking scenarios
SmartReflex voltage domain for automatic voltage scaling
Support for standby modes and separate core power domains for additional leakage power reduction
30 ARM CorePac
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