TCI6636K2H Datasheet, PDF (226/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-19 Ethernet Boot Parameter Table (Part 2 of 2)
Byte Offset Name
70
PKT PLL Cfg MSW
72
PKT PLL CFG LSW
End of Table 8-19
Description
The packet subsystem PLL configuration, MSW
The packet subsystem PLL configuration, LSW
Configured Through Boot
Configuration Pins
NO
NO
8.1.2.4.4 PCIe Boot Parameter Table
Table 8-20 PCIe Boot Parameter Table
Byte Offset
22
Name
Options
24
Address Width
26
Link Rate
28
Reference clock
30
Window 1 Size
32
Window 2 Size
34
Window 3 Size
36
Window 4 Size
38
Vendor ID
40
Device ID
42
Class code Rev ID MSW
44
Class code Rev ID LSW
46
SerDes cfg msw
48
SerDes cfg lsw
50
SerDes lane 0 cfg msw
52
SerDes lane 0 cfg lsw
54
SerDes lane 1 cfg msw
56
SerDes lane 1 cfg lsw
58
Timeout period (Secs)
End of Table 8-20
Description
Configured Through Boot
Configuration Pins
Bits 00 Mode
NO
0 = Host Mode (Direct boot mode)
1 = Boot Table Boot Mode
Bits 01 Configuration of PCIe
0 = PCIe is configured by RBL
1 = PCIe is not configured by RBL
Bit 03-02 Reserved
Bits 04 Multiplier
0 = SERDES PLL configuration is done based on SERDES register values
1 = SERDES PLL configuration based on the reference clock values
Bits 05 - 15 = Reserved
PCI address width, can be 32 or 64
YES with in conjunction
with BAR sizes
SerDes frequency, in Mbps. Can be 2500 or 5000
NO
Reference clock frequency, in units of 10 kHz. Value values are 10000
NO
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz) and
31250 (312.5 MHz). A value of 0 means that value is already in the SerDes cfg
parameters and will not be computed by the boot ROM.
Window 1size.
YES
Window 2 size.
YES
Window 3 size. Valid only if address width is 32.
YES
Window 4 Size. Valid only if the address width is 32.
YES
Vendor ID
NO
Device ID
NO
Class code revision ID MSW
NO
Class code revision ID LSW
NO
PCIe SerDes config word, MSW
NO
PCIe SerDes config word, LSW
NO
SerDes lane config word, msw lane 0
NO
SerDes lane config word, lsw, lane 0
NO
SerDes lane config word, msw, lane 1
NO
SerDes lane config word, lsw, lane 1
NO
The timeout period. Values 0 disables the time out
226 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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