TCI6636K2H Datasheet, PDF (317/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.9.2 DDR3 Slew Rate Control
The DDR3 slew rate is controlled by use of the PHY registers. See the KeyStone II DDR3 UserGuide in 2.4 ‘‘Related
Documentation from Texas Instruments’’ on page 19 for details.
10.9.3 DDR3 Memory Controller Electrical Data/Timing
The DDR3 Implementation Guidelines Application Report in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19 specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices.
The DDR3 electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed
the simulation and system characterization to ensure all DDR3 interface timings in this solution are met. Therefore,
no electrical data/timing information is supplied here for this interface.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
10.10 I²C Peripheral
The Inter-Integrated Circuit (I²C) module provides an interface between DSP and other devices compliant with
Philips Semiconductors (now NXP Semiconductors) Inter-Integrated Circuit bus specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the device through the
I²C module.
10.10.1 I²C Device-Specific Information
The device includes multiple I²C peripheral modules.
Note—When using the I²C module, ensure there are external pullup resistors on the SDA and SCL pins.
The I²C modules on the TCI6636K2H may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.),
communicate with other controllers in a system, or to implement a user interface.
The I²C port supports:
• Compatibility with Philips I²C specification revision 2.1 (January 2000)
• Fast mode up to 400 kbps (no fail-safe I/O buffers)
• Noise filter to remove noise of 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
TCI6636K2H Peripheral Information and Electrical Specifications 317