TCI6636K2H Datasheet, PDF (44/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 5-2
Terminal Functions — Signals and Control by Function (Part 7 of 19)
Signal Name
Ball No. Type IPD/IPU Description
DDR3AA00
E8
OZ
DDR3AA01
G9
OZ
DDR3AA02
G8
OZ
DDR3AA03
G10
OZ
DDR3AA04
F9
OZ
DDR3AA05
F8
OZ
DDR3AA06
C9
OZ
DDR3AA07
DDR3AA08
D9
OZ
B9
OZ
DDR3A EMIF address bus
DDR3AA09
D8
OZ
DDR3AA10
F10
OZ
DDR3AA11
A9
OZ
DDR3AA12
E10
OZ
DDR3AA13
A10
OZ
DDR3AA14
B10
OZ
DDR3AA15
D10
OZ
DDR3ACAS
C13
OZ
DDR3A EMIF column address strobe
DDR3ARAS
A14
OZ
DDR3A EMIF row address strobe
DDR3AWE
F12
OZ
DDR3A EMIF write enable
DDR3ACKE0
G12
OZ
DDR3A EMIF clock enable0
DDR3ACKE1
A11
OZ
DDR3A EMIF clock enable1
DDR3ACLKOUTP0
A12
OZ
DDR3ACLKOUTN0 B12
OZ
DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM) for Rank0
DDR3ACLKOUTP1
A13
OZ
DDR3ACLKOUTN1 B13
OZ
DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM) for Rank1
DDR3AODT0
E12
OZ
DDR3A EMIF on die termination outputs used to set termination on the SDRAMs for Rank0
DDR3AODT1
G13
OZ
DDR3A EMIF on die termination outputs used to set termination on the SDRAMs for Rank1
DDR3ARESET
B14
OZ
DDR3A reset signal
DDR3ARZQ0
H16
A
PTV compensation pin for DDR3A
DDR3ARZQ1
H10
A
PTV compensation pin for DDR3A
DDR3ARZQ2
H22
A
PTV compensation pin for DDR3A
DDR3B
DDR3BDQM0
N39
OZ
DDR3BDQM1
P34
OZ
DDR3BDQM2
U39
OZ
DDR3BDQM3
U32
OZ
DDR3BDQM4
AG33 OZ
DDR3B EMIF data masks
DDR3BDQM5
AG39 OZ
DDR3BDQM6
AK34 OZ
DDR3BDQM7
AM39 OZ
DDR3BDQM8
AE37 OZ
44 Terminals
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