TCI6636K2H Datasheet, PDF (214/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
I²C Master Mode
In master mode, the I²C device configuration uses ten bits of device configuration instead of seven as used in other
boot modes. In this mode, the device makes the initial read of the I²C EEPROM while the PLL is in bypass mode.
The initial read contains the desired clock multiplier, which must be set up prior to any subsequent reads.
Figure 8-4
I²C Master Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12
11
10
9
8
7
65 4 321
0
Reserved
Bus Addr
Param ldx/Offset
Boot Master
Reserved
Port Min
001
Lendian
Table 8-6
I²C Master Mode Device Configuration Field Descriptions
Bit Field
Description
16-14 Reserved
13-12 Bus Addr
Reserved
I²C bus address slave device
0 = I²C slave boot bus address is 0x50 (default)
1 = I²C slave boot bus address is 0x51
2 = I²C slave boot bus address is 0x52
3 = I²C slave boot bus address is 0x53
11-9 Param Idx/Offset Parameter Table Index: 0-7
This value specifies the parameter table index when the C66x is the boot master
This value specifies the start read address at 8K times this value when the ARM is the boot master
8
Boot Master
Boot Master select
0 = ARM is boot master
1 = C66x is boot master
7
Reserved
6-5 Port
Reserved
I²C port number
0 = I²C0 (default)
1 = I²C1
2 = I²C2
3 = Reserved
4
Min
Minimum boot configuration select bit.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for
configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1]
001 = I²C Master
Others = Other boot modes
0
Lendian
End of Table 8-6
Endianess
0 = Big endian
1 = Little endian
8.1.2.2.3 SPI Boot Device Configuration
Figure 8-5 SPI Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15 14 13 12 11
10
9
8
7
65 4 321
0
Width
Csel
Mode
Param ldx/Offset
Boot Master
Npin Port Min
010
Lendian
214 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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