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| TCI6636K2H Datasheet, PDF (318/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC) | |||
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TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835FâOctober 2013
Figure 10-34 shows a block diagram of the I2C module.
Figure 10-34 I2C Module Block Diagram
I2C Module
Clock
Prescale
I2CPSC
Peripheral Clock
(CPU/6)
SCL
I2C Clock
Noise
Filter
SDA
I2C Data
Noise
Filter
Bit Clock
Generator
I2CCLKH
I2CCLKL
Transmit
I2CXSR
Transmit
Shift
I2CDXR
Transmit
Buffer
Receive
I2CDRR
Receive
Buffer
I2CRSR
Receive
Shift
Control
I2COAR
I2CSAR
Own
Address
Slave
Address
I2CMDR Mode
I2CCNT
I2CEMDR
Data
Count
Extended
Mode
Interrupt/DMA
I2CIMR
I2CSTR
I2CIVR
Interrupt
Mask/Status
Interrupt
Status
Interrupt
Vector
Shading denotes control/status registers.
10.10.2 I2C Peripheral Register Description
Table 10-38 I2C Registers (Part 1 of 2)
Hex Address Offsets
Acronym
0x0000
ICOAR
0x0004
ICIMR
0x0008
ICSTR
0x000C
ICCLKL
0x0010
ICCLKH
0x0014
ICCNT
0x0018
ICDRR
0x001C
ICSAR
0x0020
ICDXR
0x0024
ICMDR
0x0028
ICIVR
0x002C
ICEMDR
0x0030
ICPSC
Register Name
I2C Own Address Register
I2C Interrupt Mask/status Register
I2C Interrupt Status Register
I2C Clock Low-time Divider Register
I2C Clock High-time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
318 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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