TCI6636K2H Datasheet, PDF (210/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
• Secure ROM Boot when the ARM CorePac0 is the boot master — The C66x CorePac0 and the ARM CorePac
Core0 are released from reset simultaneously and begin executing from secure ROM. The ARM CorePac
Core0 initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on
the bootloaded image for the C66x CorePacs and ARM CorePac prior to beginning execution.
The boot process performed by the C66x CorePac0 and the ARM CorePac Core0 in public ROM boot and secure
ROM boot are determined by the BOOTMODE[15:0] value in the DEVSTAT register. The C66x CorePac0 and the
ARM CorePac Core0 read this value, and then execute the associated boot process in software. Bit 8 determines
whether the boot is C66x CorePac boot or ARM CorePac boot. The figure below shows the bits associated with
BOOTMODE[15:0] (DEVSTAT[16:1]) when the C66x CorePac or ARM CorePac is the boot master. Note that
Figure 8-1 does not include bit 0 of the DEVSTAT contents. Bit 0 is used to select overall system endianess that is
independent of the boot mode.
The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error occurs.
The PLL settings are shown at the end of this section, and the PLL set-up details can be found in Section 10.5 ‘‘Main
PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers’’ on page 292.
Note—It is important to keep in mind that BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits of the
DEVSTAT register.
Figure 8-1 DEVSTAT Boot Mode Pins ROM Mapping
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13
12 11 10 9
8
7
6 5 4 321
X
X0
SlaveAddr 1
X
XX
Width
Csel
ARMEN SYSEN
Port
Bus Addr
Mode
ARM PLL CONFIG
Param ldx
SYS PLL CONFIG
X
Port
Npin
000
000
Min
001
010
ARM PLL CONFIG
0 Base Addr Wait Width
X
Chip Sel
ARM PLL CONFIG
1
First Block
Clear
X
Chip Sel
0
011
Lane
X
Ref Clock
Data Rate
ARM PLL CONFIG
Lane Setup
Boot Master
Min 1 0 0
PA clk Ref clk
Ext Con
ARM PLL CONFIG
Rsvd Lane Setup
SYS PLL CONFIG
101
Ref clk
Bar Config
ARM PLL CONFIG
SerDes Cfg
0 110
Port
Ref clk
Data Rate
ARM PLL CONFIG
SerDes Cfg
1 110
X
XX
X
ARM PLL CONFIG
Port
X
XX
X
X
XX
Min 1 1 1
Mode
SLEEP
I²C SLAVE
I²C MASTER
SPI
EMIF (ARM Master)
EMIF (DSP Master)
NAND (ARM Master)
NAND (DSP Master)
SRIO (ARM Master)
SRIO (DSP Master)
Ethernet (ARM Master)
Ethernet (DSP Master)
PCIe (ARM Master)
PCIe (DSP Master)
HyperLink (ARM Master)
HyperLink (DSP Master)
UART (ARM Master)
UART (DSP Master)
210 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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