TCI6636K2H Datasheet, PDF (291/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-11 Reset Switching Characteristics ⁽¹⁾
(see Figure 10-4 and Figure 10-5)
No.
Parameter
RESETFULL Pin Reset
3 td(RESETFULLH-RESETSTATH) Delay time - RESETSTAT high after RESETFULL high
4 td(RESETH-RESETSTATH)
End of Table 10-11
Soft/Hard Reset
Delay time - RESETSTAT high after RESET high
1 C = 1/SYSCLK1 clock frequency in ns
Min
Max
Unit
50000C ns
50000C ns
Figure 10-4 RESETFULL Reset Timing
POR
1
RESETFULL
RESET
RESETSTAT
Figure 10-5 Soft/Hard Reset Timing
POR
RESETFULL
2
RESET
RESETSTAT
Table 10-12 Boot Configuration Timing Requirements ⁽¹⁾
See Figure 10-6)
No.
1 tsu(GPIOn-RESETFULL)
2 th(RESETFULL-GPIOn)
End of Table 10-12
1 C = 1/SYSCLK1 clock frequency in ns.
Setup time - GPIO valid before RESETFULL asserted
Hold time - GPIO valid after RESETFULL asserted
3
4
Min
Max
Unit
12C
ns
12C
ns
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TCI6636K2H Peripheral Information and Electrical Specifications 291