TCI6636K2H Datasheet, PDF (206/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
7.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User-programmable priority
registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means
higher priority — PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include the
C66x CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA-based
peripherals also have internal registers to define the priority level of their initiated transactions.
The Packet DMA secondary port is one master port that does not have priority allocation register inside the
Multicore Navigator. The priority level for transaction from this master port is described by the QM_PRIORITY bit
field in the CHIP_MISC_CTL0 register shown in Figure 8-34 and Table 8-52.
For all other modules, see the respective User Guides in 2.4 ‘‘Related Documentation from Texas Instruments’’ on
page 19 for programmable priority registers.
206 System Interconnect
Copyright 2013 Texas Instruments Incorporated
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