TCI6636K2H Datasheet, PDF (13/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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DDR3 PLL DDRCLK(N|P) Timing
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
PASS PLL Clock Domain Module Internal Clock
Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
PASS PLL Control Register 0 Field Descriptions
(PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
PASS PLL Control Register 1 Field Descriptions
(PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
PASS PLL Timing Requirements . . . . . . . . . . . . 314
NMI and LRESET Timing Requirements . . . . . 314
I²C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
I²C Timing Requirements . . . . . . . . . . . . . . . . . . 319
I²C Switching Characteristics. . . . . . . . . . . . . . . 320
SPI Timing Requirements . . . . . . . . . . . . . . . . . . 321
SPI Switching Characteristics. . . . . . . . . . . . . . . 321
HyperLink Peripheral Timing Requirements 324
HyperLink Peripheral Switching
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
UART Timing Requirements. . . . . . . . . . . . . . . . 326
UART Switching Characteristics . . . . . . . . . . . . 327
MACID1 Register Field Descriptions . . . . . . . . 328
MACID2 Register Field Descriptions . . . . . . . . 328
RFTCLK Select Register Field Descriptions . . 329
MDIO Timing Requirements . . . . . . . . . . . . . . . 330
MDIO Switching Characteristics . . . . . . . . . . . . 330
Timer Input Timing Requirements . . . . . . . . . 331
TCI6636K2H
SPRS835F—February 2012—Revised October 2013
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Table 12-1
Timer Output Switching Characteristics . . . . .331
GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
GPIO Input Timing Requirements . . . . . . . . . .334
GPIO Output Switching Characteristics . . . . .334
AIF2 Timer Module Timing Requirements . . .335
AIF2 Timer Module Switching
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
EMIF16 Asynchronous Memory Timing
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
ICEPick Debug Secondary TAPs . . . . . . . . . . . . .345
Emulation Interface with Different Debug Port
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
MSTID mapping for Hardware Instrumentation
(CPTRACERS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
MSTID Mapping for Software Messages . . . . .348
Cross-Triggering Connection . . . . . . . . . . . . . . .349
TI XTRIG Assignment . . . . . . . . . . . . . . . . . . . . . . .349
Peripherals Emulation Support . . . . . . . . . . . . .350
EMUSUSP Peripheral Summary (for EMUSUSP
handshake from DEBUGSS) . . . . . . . . . . . . . . . . .351
EMUSUSP Core Summary (for EMUSUSP
handshake to DEBUGSS) . . . . . . . . . . . . . . . . . . .351
Trace Switching Characteristics . . . . . . . . . . . . .352
JTAG Test Port Timing Requirements . . . . . . .353
JTAG Test Port Switching Characteristics . . . .353
Thermal Resistance Characteristics (PBGA
Package) AAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.