TCI6636K2H Datasheet, PDF (303/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-24 Reset Isolation Register Field Descriptions
Bit Field
Description
31-10 Reserved
Reserved.
9
SRIOISO
Isolate SRIO module control
0 = Not reset isolated
1 = Reset isolated
8
SRISO
Isolate SmartReflex control
0 = Not reset isolated
1 = Reset isolated
7-4 Reserved
Reserved
3
AIF2ISO
Isolate AIF2 module control
0 = Not reset isolated
1 = Reset isolated
2-0 Reserved
End of Table 10-24
Reserved
10.5.3 Main PLL Control Registers
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the Main PLL
Controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write
to these registers, software should go through an unlocking sequence using the KICK0 and KICK1 registers. These
registers reset only on a POR reset.
For valid configurable values of the MAINPLLCTL registers, see Section 8.1.4 ‘‘System PLL Settings’’ on page 231.
See Section 8.2.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 240 for the address location of the
KICK registers and their locking and unlocking sequences.
See Figure 10-17 and Table 10-25 for MAINPLLCTL0 details and Figure 10-18 and Table 10-26 for MAINPLLCTL1
details.
Figure 10-17 Main PLL Control Register 0 (MAINPLLCTL0)
31
24
23
19
BWADJ[7:0]
Reserved
RW-0000 0101
RW - 0000 0
Legend: RW = Read/Write; -n = value after reset
18
12
PLLM[12:6]
RW-0000000
11
6
Reserved
RW-000000
5
0
PLLD
RW-000000
Table 10-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions (Part 1 of 2)
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7.
23-19 Reserved
Reserved
18-12 PLLM[12:6]
7-bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the multiply
factor minus 1.
The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the PLLM[12:6] bits
are controlled by the above chip-level register. MAINPLLCTL0 register PLLM[12:6] bits should be written just before
writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO
operation is initiated in the PLL controller. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in
2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19for the recommended programming sequence.
Output Divide ratio and Bypass enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL
Controller. See the “PLL Secondary Control Register (SECCTL)” on page 298 for more details.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 303