TCI6636K2H Datasheet, PDF (335/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.27 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the C66x CorePacs.
The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is
not broken. The Semaphore module has unique interrupts to each of the C66x CorePacs to identify when that
CorePac has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to
allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports three masters and contains 32 semaphores that can be shared within the system.
There are two methods of accessing a semaphore resource:
• Direct Access: A C66x CorePac directly accesses a semaphore resource. If free, the semaphore is granted. If
not free, the semaphore is not granted.
• Indirect Access: A C66x CorePac indirectly accesses a semaphore resource by writing to it. Once the resource
is free, an interrupt notifies the C66x CorePac that the resource is available.
10.28 Antenna Interface Subsystem 2 (AIF2)
The AIF2 transfers data between the external RF units and the C66x CorePacs, RAC, TAC, and the FFTC modules
via the TeraNet. The external AIF2 interface connects the AIF2 with either RF units and/or other baseband
OBSAI/CPRI devices. The AIF2 has 24 timer synchronization events from the AIF2 Timer (AT) module:
• Timer synchronization events 0-3 are routed as primary events to the EDMA3CC1 and also as secondary
events to the C66x CorePacs via CIC2.
• Timer synchronization events 3-7 are routed as primary events to the EDMA3CC2.
• Timer synchronization events 8, 9, 10, 11 and 12 are hard-wired to TAC, RAC_0, RAC_1 respectively.
Table 10-57 AIF2 Timer Module Timing Requirements (Part 1 of 2)
See Figure 10-51, Figure 10-54, Figure 10-55, and Figure 10-56
No.
RP1 Clock and Frameburst
1 tc(RP1CLKN)
Cycle time, RP1CLK(N)
1 tc(RP1CLKP)
Cycle time, RP1CLK(P)
2 tw(RP1CLKNL)
Pulse duration, RP1CLK(N) low
3 tw(RP1CLKNH)
Pulse duration, RP1CLK(N) high
3 tw(RP1CLKPL)
Pulse duration, RP1CLK(P) low
2 tw(RP1CLKPH)
Pulse duration, RP1CLK(P) high
4 tr(RP1CLKN)
Rise time - RP1CLKN 10% to 90%
4 tf(RP1CLKN)
Fall time - RP1CLKN 90% to 10%
4 tr(RP1CLKP)
Rise time - RP1CLKP 10% to 90%
4 tf(RP1CLKP)
Fall time - RP1CLKP 90% to 10%
5 tj(RP1CLKN)
Period jitter (peak-to-peak), RP1CLK(N)
5 tj(RP1CLKP)
Period jitter (peak-to-peak), RP1CLK(P)
6 tw(RP1FBN)
Bit period, RP1FB(N)
6 tw(RP1FBP)
Bit period, RP1FB(P)
7 tr(RP1CLKN)
Rise time - RP1FBN 10% to 90%
7 tf(RP1CLKN)
Fall time - RP1FBN 90% to 10%
7 tr(RP1CLKP)
Rise time - RP1FBP 10% to 90%
7 tf(RP1CLKP)
Fall time - RP1FBP 90% to 10%
Min
Max
Unit
32.55
32.55
ns
32.55
32.55
ns
0.4 * C1 ⁽¹⁾
0.6 * C1
ns
0.4 * C1
0.6 * C1
ns
0.4 * C1
0.6 * C1
ns
0.4 * C1
0.6 * C1
ns
350.00
ps
350.00
ps
350.00
ps
350.00
ps
600
ps
600
ps
8 * C1
8 * C1
ns
8 * C1
8 * C1
ns
350.00
ps
350.00
ps
350.00
ps
350.00
ps
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TCI6636K2H Peripheral Information and Electrical Specifications 335