TCI6636K2H Datasheet, PDF (216/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-8
EMIF Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Boot Devices
Boot Devices[16] used conjunction with Boot Devices[4] and Boot Devices [Used in conjunction with bits 3-1]
0 = EMIF boot mode
1 = Other boot modes
15-14 Base Addr
Base address (0-3) used to calculate the branch address. Branch address is the chip select plus Base Address
*16MB
13
Wait
Extended Wait
0 = Extended Wait disabled
1 = Extended Wait enabled
12
Width
EMIF Width
0 = 8-bit EMIF Width
1 = 16-bit EMIF Width
11-9 Chip Sel/ARM PLL
Setting
When Boot Master = 0 (ARM is Boot Master), Pin[11:9] used as ARM PLL Setting and the chip select region CS0 is
used. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting
for the device. Table 8-27 shows settings for various input clock frequencies.
When Boot Master =1 (C66x is Boot Master), Pin[10:9] used as Chip Sel that specifies the chip select region,
CS0-CS3.
00 = CS0 (EMIFCE0)
01 = CS1 (EMIFCE1)
10 = CS2 (EMIFCE2)
11 = CS3 (EMIFCE3)
8
Boot Master
Boot Master select
0 = ARM is boot master
1 = C66x is boot master
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the
device. Table 8-27 shows settings for various input clock frequencies.
4
Boot Devices
Boot Devices[4] used conjunction with Boot Devices[16] and Boot Devices [Use din conjunction with bits 3-1]
0 = EMIF boot mode
1 = Other boot modes
3-1
Boot Devices
Boot Devices[3:1] used in conjunction with Boot Device [4]
011 = EMIF boot mode
Others = Other boot modes
0
Lendian
End of Table 8-8
Endianess
0 = Big endian
1 = Little endian
8.1.2.2.5 NAND Boot Device Configuration
Figure 8-7 NAND Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13
12
11 10
9
8
765
1
First Block
Clear X
Chip Sel
Boot Master=1
Sys PLL Cfg
1
First Block
Clear
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
4 321
Min
011
Min
011
0
Lendian
Lendian
216 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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