TCI6636K2H Datasheet, PDF (26/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 3-1.
Table 3-1
AIDx ⁽¹⁾ Bit
Available Memory Page Protection Schemes
Local Bit
Description
0
0
No access to memory page is permitted.
0
1
Only direct access by DSP is permitted.
1
0
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1
1
End of Table 3-1
All accesses permitted.
1 x = 0, 1, 2, 3, 4, 5
Faults are handled by software in an interrupt (or an exception, programmable within the CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return 0, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal the event to the DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
3.3 Bandwidth Management
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to
the highest priority requestor. The following four resources are managed by the bandwidth management control
hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
The priority level for operations initiated within the C66x CorePac are declared through registers in the CorePac.
These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the CorePac by system peripherals is declared through the Priority
Allocation Register (PRI_ALLOC). System peripherals with no fields in PRI_ALLOC have their own registers to
program their priorities.
More information on the bandwidth management features of the CorePac can be found in the C66x CorePac
Reference Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
26 C66x CorePac
Copyright 2013 Texas Instruments Incorporated
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