TCI6636K2H Datasheet, PDF (121/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-23 System Event Mapping — ARM CorePac Interrupts (Part 9 of 12)
Event No. Event Name
Description
346
EDMACC_3_TC_4_INT
EDMA3CC3 individual completion interrupt
347
EDMACC_3_TC_5_INT
EDMA3CC3 individual completion interrupt
348
EDMACC_3_TC_6_INT
EDMA3CC3 individual completion interrupt
349
EDMACC_3_TC_7_INT
EDMA3CC3 individual completion interrupt
350
EDMACC_4_GINT
EDMA3CC4 global completion interrupt
351
EDMACC_4_TC_0_INT
EDMA3CC4 individual completion interrupt
352
EDMACC_4_TC_1_INT
EDMA3CC4 individual completion interrupt
353
EDMACC_4_TC_2_INT
EDMA3CC4 individual completion interrupt
354
EDMACC_4_TC_3_INT
EDMA3CC4 individual completion interrupt
355
EDMACC_4_TC_4_INT
EDMA3CC4 individual completion interrupt
356
EDMACC_4_TC_5_INT
EDMA3CC4 individual completion interrupt
357
EDMACC_4_TC_6_INT
EDMA3CC4 individual completion interrupt
358
EDMACC_4_TC_7_INT
EDMA3CC4 individual completion interrupt
359
SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS Error interrupt
360
SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
361
SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
362
SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
363
SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
364
SR_0_VPNOSMPSACK
SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time
interval
365
SR_0_VPEQVALUE
SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS
voltage
366
SR_0_VPMAXVDD
SmartReflex The new voltage required is equal to or greater than MaxVdd
367
SR_0_VPMINVDD
SmartReflex The new voltage required is equal to or less than MinVdd
368
SR_0_VPINIDLE
SmartReflex. Indicating that the FSM of voltage processor is in idle
369
SR_0_VPOPPCHANGEDONE
SmartReflex Indicating that the average frequency error is within the desired limit
370
SR_0_VPSMPSACK
SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
371
SR_0_SR_TEMPSENSOR
SmartReflex temperature threshold crossing interrupt
372
SR_0_SR_TIMERINT
Smart Reflex internal timer expiration interrupt
373
SR_1_PO_VCON_SMPSERR_INT SmartReflex SMPS Error interrupt
374
SR_1_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
375
SR_1_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
376
SR_1_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
377
SR_1_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
378
SR_1_VPNOSMPSACK
SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time
interval
379
SR_1_VPEQVALUE
SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS
voltage
380
SR_1_VPMAXVDD
SmartReflex The new voltage required is equal to or greater than MaxVdd
381
SR_1_VPMINVDD
SmartReflex The new voltage required is equal to or less than MinVdd
382
SR_1_VPINIDLE
SmartReflex. Indicating that the FSM of voltage processor is in idle
383
SR_1_VPOPPCHANGEDONE
SmartReflex Indicating that the average frequency error is within the desired limit
384
SR_1_VPSMPSACK
SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
385
SR_1_SR_TEMPSENSOR
SmartReflex temperature threshold crossing interrupt
386
SR_1_SR_TIMERINT
Smart Reflex internal timer expiration interrupt
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Memory, Interrupts, and EDMA for TCI6636K2H 121