TCI6636K2H Datasheet, PDF (343/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.35.1 Chip Level Features
– Support for 1149.1(JTAG and Boundary scan) and 1149.6 (Boundary scan extensions).
– Trace sources to DEBUG SubSystem System Trace Module (DEBUGSS STM)
› Provides a way for hardware instrumentation and software messaging to supplement the processor
core trace mechanisms.
› Hardware instrumentation support of CPTracers to support logging of bus transactions for critical
endpoints
› Software messaging/instrumentation support for DSP and QMSS PDSP cores through DEBUGSS
STM.
– Trace Sinks
› Support for trace export (from all processor cores and DEBUGSS STM) through emulation pins.
Concurrent trace of DSP and STM traces or ARM and STM traces via EMU pins is possible.
Concurrent trace export of DSP and ARM is not possible via EMU pins.
– Support for 32KB DEBUGSS TBR (Trace Buffer and Router) to hold system trace. The data can be drained
using EDMA to on-chip or DDR memory buffers. These intermediate buffers can subsequently be drained
through the device high speed interfaces. The DEBUGSS TBR is dedicated to the DEBUGSS STM
module.The trace draining interface used in KeyStone II for DEBUGSS and ARMSS are based on the new
CT-TBR. Cross triggering: Provides a way to propagate debug (trigger) events from one
processor/subsystem/module to another
› Cross triggering between multiple devices via EMU0/EMU1 pins
› Cross triggering between multiple processing cores within the device like ARM/DSP Cores and
non-processor entities like ARM STM (input only), CPTracers, CT-TBRs and DEBUGSS STM (input
only)
– Synchronized starting and stopping of processing cores
› Global start of all ARM cores
› Global start of all DSP cores
› Global stopping of all ARM and DSP cores
– Emulation mode aware peripherals (suspend features and debug access features)
– Support system memory access via the DAP port (natively support 32-bit address, and it can support
36-bit address through configuration of MPAX inside MSMC). Debug access to any invalid memory
location (reserved/clock-gated/power-down) shall not cause system hang.
– Scan access to secondary TAPs of DEBUGSS shall be disabled in Secure devices by default. Security
override sequence shall be supported (requires software override sequence) to enable debug in secure
devices. In addition, Debug features of the ARM cores are blockable through the ARM debug
authentication interface in secure devices.
– Support WIR (wait-in-reset) debug boot mode for Non-secure devices.
– Debug functionality shall survive all pin resets except power-on resets (POR/RESETFULL) and test reset
(TRST).
– PDSP Debug features like access/control through DAP, Halt mode debug and software instrumentation.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 343