TCI6636K2H Datasheet, PDF (90/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-1
Device Memory Map Summary for TCI6636K2H (Part 10 of 12)
Physical 40 bit Address
Start
End
Bytes
ARM View
DSP View
00 0BC0 0000 00 0BCF FFFF 1M
Multicore shared memory
controller (MSMC) config
Multicore shared memory
controller (MSMC) config
00 0BD0 0000 00 0BFF FFFF 3M
Reserved
Reserved
00 0C00 0000 00 0C5F FFFF 6M
Multicore shared memory (MSM) Multicore shared memory
(MSM)
00 0C60 0000 00 0FFF FFFF 58M
Reserved
Reserved
00 1000 0000 00 107F FFFF 8M
Reserved
Reserved
00 1080 0000 00 108F FFFF 1M
CorePac0 L2 SRAM
CorePac0 L2 SRAM
00 1090 0000 00 10DF FFFF 5M
Reserved
Reserved
00 10E0 0000 00 10E0 7FFF 32K
CorePac0 L1P SRAM
CorePac0 L1P SRAM
00 10E0 8000 00 10EF FFFF 1M-32K Reserved
Reserved
00 10F0 0000 00 10F0 7FFF 32K
CorePac0 L1D SRAM
CorePac0 L1D SRAM
00 10F0 8000 00 117F FFFF 9M-32K Reserved
Reserved
00 1180 0000 00 118F FFFF 1M
CorePac1 L2 SRAM
CorePac1 L2 SRAM
00 1190 0000 00 11DF FFFF 5M
Reserved
Reserved
00 11E0 0000 00 11E0 7FFF 32K
CorePac1 L1P SRAM
CorePac1 L1P SRAM
00 11E0 8000 00 11EF FFFF 1M-32K Reserved
Reserved
00 11F0 0000 00 11F0 7FFF 32K
CorePac1 L1D SRAM
CorePac1 L1D SRAM
00 11F0 8000 00 127F FFFF 9M-32K Reserved
Reserved
00 1280 0000 00 128F FFFF 1M
CorePac2 L2 SRAM
CorePac2 L2 SRAM
00 1290 0000 00 12DF FFFF 5M
Reserved
Reserved
00 12E0 0000 00 12E0 7FFF 32K
CorePac2 L1P SRAM
CorePac2 L1P SRAM
00 12E0 8000 00 12EF FFFF 1M-32K Reserved
Reserved
00 12F0 0000 00 12F0 7FFF 32K
CorePac2 L1D SRAM
CorePac2 L1D SRAM
00 12F0 8000 00 137F FFFF 9M-32K Reserved
Reserved
00 1380 0000 00 1388 FFFF 1M
CorePac3 L2 SRAM
CorePac3 L2 SRAM
00 1390 0000 00 13DF FFFF 5M
Reserved
Reserved
00 13E0 0000 00 13E0 7FFF 32K
CorePac3 L1P SRAM
CorePac3 L1P SRAM
00 13E0 8000 00 13EF FFFF 1M-32K Reserved
Reserved
00 13F0 0000 00 13F0 7FFF 32K
CorePac3 L1D SRAM
CorePac3 L1D SRAM
00 13F0 8000 00 147F FFFF 9M-32K Reserved
Reserved
00 1480 0000 00 148F FFFF 1M
CorePac4 L2 SRAM
CorePac4 L2 SRAM
00 1490 0000 00 14DF FFFF 5M
Reserved
Reserved
00 14E0 0000 00 14E0 7FFF 32K
CorePac4 L1P SRAM
CorePac4 L1P SRAM
00 14E0 8000 00 14EF FFFF 1M-32K Reserved
Reserved
00 14F0 0000 00 14F0 7FFF 32K
CorePac4 L1D SRAM
CorePac4 L1D SRAM
00 14F0 8000 00 157F FFFF 9M-32K Reserved
Reserved
00 1580 0000 00 158F FFFF 1M
CorePac5 L2 SRAM
CorePac5 L2 SRAM
00 1590 0000 00 15DF FFFF 5M
Reserved
Reserved
00 15E0 0000 00 15E0 7FFF 32K
CorePac5 L1P SRAM
CorePac5 L1P SRAM
00 15E0 8000 00 15EF FFFF 1M-32K Reserved
Reserved
00 15F0 0000 00 15F0 7FFF 32K
CorePac5 L1D SRAM
CorePac5 L1D SRAM
00 15F0 8000 00 167F FFFF 9M-32K Reserved
Reserved
SOC View
Multicore shared memory
controller (MSMC) config
Reserved
Multicore shared memory
(MSM)
Reserved
Reserved
CorePac0 L2 SRAM
Reserved
CorePac0 L1P SRAM
Reserved
CorePac0 L1D SRAM
Reserved
CorePac1 L2 SRAM
Reserved
CorePac1 L1P SRAM
Reserved
CorePac1 L1D SRAM
Reserved
CorePac2 L2 SRAM
Reserved
CorePac2 L1P SRAM
Reserved
CorePac2 L1D SRAM
Reserved
CorePac3 L2 SRAM
Reserved
CorePac3 L1P SRAM
Reserved
CorePac3 L1D SRAM
Reserved
CorePac4 L2 SRAM
Reserved
CorePac4 L1P SRAM
Reserved
CorePac4 L1D SRAM
Reserved
CorePac5 L2 SRAM
Reserved
CorePac5 L1P SRAM
Reserved
CorePac5 L1D SRAM
Reserved
90 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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