TCI6636K2H Datasheet, PDF (307/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-29 Main PLL Controller/ARM/SRIO/HyperLink/PCIe/USB Clock Input Timing Requirements ⁽¹⁾ (Part 3 of 3)
(see Figure 10-21 through Figure 10-24)
No.
Min
Max Unit
5 tj(SRIOSGMIICLKP)
Jitter, RMS SRIOSGMIICLKP
2 ps, RMS
5 tj(SRIOSGMIICLKN)
Jitter, RMS SRIOSGMIICLKN (SRIO not used)
4 ps, RMS
5 tj(SRIOSGMIICLKP)
Jitter, RMS SRIOSGMIICLKP (SRIO not used)
4 ps, RMS
HYPxCLK[P:N]
1 tc(HYPCLKN)
Cycle time HYPCLKN cycle time
3.2 or 4 or 6.4
ns
1 tc(HYPCLKP)
Cycle time HYPCLKP cycle time
3.2 or 4 or 6.4
ns
3 tw(HYPCLKN)
Pulse width HYPCLKN high
0.45*tc(HYPCLKN)
0.55*tc(HYPCLKN)
ns
2 tw(HYPCLKN)
Pulse width HYPCLKN low
0.45*tc(HYPCLKN)
0.55*tc(HYPCLKN)
ns
2 tw(HYPCLKP)
Pulse width HYPCLKP high
0.45*tc(HYPCLKP)
0.55*tc(HYPCLKP)
ns
3 tw(HYPCLKP)
Pulse width HYPCLKP low
0.45*tc(HYPCLKP)
0.55*tc(HYPCLKP)
ns
4 tr(HYPCLK)
Rise time HYPCLK differential rise time (10% to
90%)
0.2*tc(HYPCLKP)
ps
4 tf(HYPCLK)
Fall time HYPCLK differential fall time (10% to
90%)
0.2*tc(HYPCLKP)
ps
5 tj(HYPCLKN)
Jitter, RMS HYPCLKN
4 ps, RMS
5 tj(HYPCLKP)
Jitter, RMS HYPCLKP
4 ps, RMS
PCIECLK[P:N]
1 tc(PCIECLKN)
Cycle time PCIECLKN cycle time
3.2 or 4 or 6.4 or 10
ns
1 tc(PCIECLKP)
Cycle time PCIECLKP cycle time
3.2 or 4 or 6.4 or 10
ns
3 tw(PCIECLKN)
Pulse width PCIECLKN high
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2 tw(PCIECLKN)
Pulse width PCIECLKN low
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2 tw(PCIECLKP)
Pulse width PCIECLKP high
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
3 tw(PCIECLKP)
Pulse width PCIECLKP low
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
4 tr(PCIECLK)
Rise time PCIECLK differential rise time (10% to
90%)
0.2*tc(PCIECLKP)
ps
4 tf(PCIECLK)
Fall time PCIECLK differential fall time (10% to
90%)
0.2*tc(PCIECLKP)
ps
5 tj(PCIECLKN)
Jitter, RMS PCIECLKN
4 ps, RMS
5 tj(PCIECLKP)
Jitter, RMS PCIECLKP
4 ps, RMS
USBCLK[P:M]
1 tc(USBCLKN)
Cycle time USBCLKM cycle time
5
50
ns
1 tc(USBCLKP)
Cycle time USBCLKP cycle time
5
50
ns
3 tw(USBCLKN)
Pulse width USBCLKM high
0.45*tc(USBCLKN)
0.55*tc(USBCLKN)
ns
2 tw(USBCLKN)
Pulse width USBCLKM low
0.45*tc(USBCLKN)
0.55*tc(USBCLKN)
ns
2 tw(USBCLKP)
Pulse width USBCLKP high
0.45*tc(USBCLKP)
0.55*tc(USBCLKP)
ns
3 tw(USBCLKP)
Pulse width USBCLKP low
0.45*tc(USBCLKP)
0.55*tc(USBCLKP)
ns
4 tr(USBCLK)
Rise time USBCLK differential rise time (10% to
90%)
TBD
ps
4 tf(USBCLK)
Fall time USBCLK differential fall time (10% to
90%)
TBD
ps
5 tj(USBCLKN)
Jitter, RMS USBCLKM
3 ps, RMS
5 tj(USBCLKP)
End of Table 10-29
Jitter, RMS USBCLKP
3 ps, RMS
1 See the Hardware Design Guide for KeyStone II Devices (in development) for detailed recommendations.
2 If AIF2 is being used then SYSCLK(N|P) can be programmed only to fixed values, if AIF2 is not being used then any value in the range between the min and max values can be
used.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 307