TCI6636K2H Datasheet, PDF (257/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-52 Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions (Part 2 of 2)
Bit Field
12 MSMC_BLOCK_PARITY_RST
11-3 Reserved
2-0 QM_PRIORITY
End of Table 8-52
Description
Controls MSMC parity RAM reset. When set to ‘1’ means the MSMC parity RAM will not be reset.
Reserved
Control the priority level for the transactions from QM_Master port, which access the external linking RAM.
8.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
Figure 8-35 Chip Miscellaneous Control Register (CHIP_MISC_CTL1)
31
15
14
13
12
0
Reserved
IO_TRACE_SEL
ARM_PLL_EN
Reserved
R- 0000 0000 00000000
RW-0
RW-0
RW-0000000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 8-53 Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions
Bit
31-15
14
Field
Reserved
IO_TRACE_SEL
13 ARM_PLL_EN
12-0 Reserved
End of Table 8-53
Description
Reserved.
This bit controls the pin muxing of GPIO[31:17] and EMU[33:19] pin
0 = GPIO[31:17] is selected
1 = EMU[33:19] pins is selected
This bit controls the glitchfree clock mux between bypass clock and ARM PLL output clock
0 = Bypass clock (default)
1 = PLL output clock
8.2.3.25 System Endian Status Register (SYSENDSTAT)
This register provides a way for reading the system endianness in an endian-neutral way. A zero value indicates big
endian and a non-zero value indicates little endian. The SYSENDSTAT register captures the LENDIAN bootmode
pin and is used by the BOOTROM to guide the bootflow. The value is latched on the rising edge of POR or
RESETFULL.
Figure 8-36 System Endian Status Register
31
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
1
0
SYSENDSTAT
R-0
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Device Boot and Configuration 257