TCI6636K2H Datasheet, PDF (287/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.4 Reset Controller
The reset controller detects the different type of resets supported on the TCI6636K2H device and manages the
distribution of those resets throughout the device. The device has the following types of resets:
• Power-on reset
• Hard reset
• Soft reset
• Local reset
Table 10-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section 10.4.8 ‘‘Reset Electrical
Data/Timing’’ on page 290.
Table 10-9 Reset Types
Type
Initiator
Effect(s)
Power-on reset
POR pin
RESETFULL pin
Resets the entire chip including the test and emulation logic. The device configuration pins are
latched only during power-on reset.
Hard reset
RESET pin
PLLCTL ⁽¹⁾ Register (RSCTRL)
Watchdog timers
Emulation
Hard reset resets everything except for test, emulation logic, and reset isolation modules. This
reset is different from power-on reset in that the PLL Controller assumes power and clocks are
stable when a hard reset is asserted. The device configurations pins are not relatched.
Emulation-initiated reset is always a hard reset.
By default, these initiators are configured as hard reset, but can be configured (except emulation)
as a soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory
can be retained during a hard reset if the SDRAM is placed in self-refresh mode.
Soft reset
RESET pin
PLLCTL Register (RSCTRL)
Watchdog timers
Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and DDR3
EMIF MMRs contents are retained.
By default, these initiators are configured as hard reset, but can be configured as soft reset in the
RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained
during a soft reset if the SDRAM is placed in self-refresh mode.
Local reset
LRESET pin
Watchdog timer timeout
LPSC MMRs
End of Table 10-9
Resets the C66x CorePac, without disturbing clock alignment or memory contents. The device
configuration pins are not relatched.
1 All masters in the device have access to the PLL Control Registers.
10.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following:
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device, including the
reset-isolated logic, when the device is already powered up. For this reason, the RESETFULL pin, unlike POR, should
be driven by the on-board host control other than the power good circuitry. For power-on reset, the Main PLL
Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or
the dividers in the PLL Controller.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 287