TCI6636K2H Datasheet, PDF (47/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 5-2
Signal Name
DDR3BD46
DDR3BD47
DDR3BD48
DDR3BD49
DDR3BD50
DDR3BD51
DDR3BD52
DDR3BD53
DDR3BD54
DDR3BD55
DDR3BD56
DDR3BD57
DDR3BD58
DDR3BD59
DDR3BD60
DDR3BD61
DDR3BD62
DDR3BD63
DDR3BCE0
DDR3BCE1
DDR3BBA0
DDR3BBA1
DDR3BBA2
DDR3BA00
DDR3BA01
DDR3BA02
DDR3BA03
DDR3BA04
DDR3BA05
DDR3BA06
DDR3BA07
DDR3BA08
DDR3BA09
DDR3BA10
DDR3BA11
DDR3BA12
DDR3BA13
DDR3BA14
DDR3BA15
DDR3BCAS
DDR3BRAS
DDR3BWE
DDR3BCKE0
DDR3BCKE1
Terminal Functions — Signals and Control by Function (Part 10 of 19)
Ball No. Type IPD/IPU Description
AH38 IOZ
AJ37 IOZ
AK39 IOZ
AK38 IOZ
AK36 IOZ
AK35 IOZ
AL34 IOZ
AL36 IOZ
AL37 IOZ
AL33 IOZ
DDR3B EMIF data bus
AN34 IOZ
AN36 IOZ
AN33 IOZ
AM34 IOZ
AM35 IOZ
AM38 IOZ
AM36 IOZ
AN37 IOZ
AB34 OZ
DDR3B EMIF chip enable
AA36 OZ
DDR3B EMIF chip enable
AA37 OZ
AA34 OZ
DDR3B EMIF bank address
AB35 OZ
AA32 OZ
W33
OZ
W32
OZ
Y34
OZ
W34
OZ
V34
OZ
W36
OZ
W37
OZ
AA33 OZ
DDR3B EMIF address bus
Y32
OZ
Y38
OZ
AA39 OZ
Y35
OZ
Y39
OZ
AA38 OZ
Y36
OZ
AC36 OZ
DDR3B EMIF column address strobe
AD32 OZ
DDR3B EMIF row address strobe
AC37 OZ
DDR3B EMIF write enable
AB39 OZ
DDR3B EMIF clock enable0
AB38 OZ
DDR3B EMIF clock enable1
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