TCI6636K2H Datasheet, PDF (345/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
• Dynamic TAP insertion
– Serially linking up to 32 TAP controllers
– Individually selecting one or more of the TAPS for scan without disrupting the instruction register (IR)
state of other TAPs
• Power, reset and clock management
– Provides the power and clock status of the domain to the debugger
– Provides debugger control of the power domain of a processor.
› Force the domain power and clocks on
› Prohibit the domain from being clock-gated or powered down
– Applies system reset
– Provides wait-in-reset (WIR) boot mode
– Provides global and local WIR release
– Provides global and local reset block
The ICEPick module implements a connect register, which must be configured with a predefined key to enable the
full set of JTAG instructions. Once the debug connect key has been properly programmed, ICEPick signals and
subsystems emulation logic should be turned on.
10.35.2.1 ICEPick Dynamic Tap Insertion
To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP router to
program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively choose which
subsystem TAPs are accessible through the device-level debug interface. Each secondary TAP can be dynamically
included in or excluded from the scan path. From external JTAG interface point of view, secondary TAPS that are
not selected appear not to exist.
There are two types of components connected through ICEPick to external debug interface:
• Legacy JTAG Components — C66x implements a JTAG-compatible port and are directly interfaced with
ICEPick and individually attached to an ICEPick secondary TAP.
• CoreSight Components — The CoreSight components are interfaced with ICEPick through the CS_DAP
module. The CS_DAP is attached to the ICEPick secondary TAP and translates JTAG transactions into APBv3
transactions.
Table 10-60 shows the ICEPick secondary taps in the system. For more details on the test related P1500 TAPs, please
refer to the DFTSS specification.
Table 10-60 ICEPick Debug Secondary TAPs (Part 1 of 2)
Tap #
0
1
2
3
4
5
6
7
8
9..13
Type
n/a
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
Name
n/a
C66x CorePac0
C66x CorePac1
C66x CorePac2
C66x CorePac3
C66x CorePac4
C66x CorePac5
C66x CorePac6
C66x CorePac7
Reserved
IR Scan
Length
n/a
38
38
38
38
38
38
38
38
NA
Access in
Secure Device Description
No
RESERVED (This is an internal TAP and not exposed at the DEBUGSS boundary)
No
C66x CorePac0
No
C66x CorePac1
No
C66x CorePac2
No
C66x CorePac3
No
C66x CorePac4
No
C66x CorePac5
No
C66x CorePac6
No
C66x CorePac7
No
Spare ports for future expansion
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
TCI6636K2H Peripheral Information and Electrical Specifications 345