TCI6636K2H Datasheet, PDF(40/362 Page) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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TCI6636K2H Datasheet, PDF (40/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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TCI6636K2H

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

SPRS835FâOctober 2013

Table 5-2

Terminal Functions â Signals and Control by Function (Part 3 of 19)

Signal Name

Ball No. Type IPD/IPU Description

BOOTCOMPLETE

AF5

OZ Down Boot progress indication output

DDR3A_REMAP_ENâ A36

I

Down Control ARM remapping of DDR3A address space in the lower 4 GB (32b space) Mode select.

Secondary function. Pin shared with GPIO16.

LENDIANâ

F29

I

Up

Little endian configuration pin. Pin shared with GPIO00

MAINPLLODSELâ

E32

I

Down Main PLL Output divider select. Pin shared with GPIO14.

Clock / Reset

ALTCORECLKN

ALTCORECLKP

AL2

I

AM2

I

Alternate clock input to Main PLL

ARMCLKN

ARMCLKP

B37

I

C37

I

Reference clock to drive ARM CorePac PLL

CORECLKSEL

AL4

I

Down Core clock select to select between SYSCLK(N|P) and ALTCORECCLK to the main PLL

CORESEL0

F24

I

Down

CORESEL1

CORESEL2

E24

I

Down

Select for the target core for LRESET and NMI

D24

I

Down

CORESEL3

G24

I

Down

DDR3ACLKN

DDR3ACLKP

A25

I

B25

I

DDR3A reference clock input to DDR PLL

DDR3BCLKN

DDR3BCLKP

AR39 I

AR38 I

DDR3B reference clock input to DDR PLL

HOUT

AE5

OZ Up

Interrupt output pulse created by IPCGRH

HYP0CLKN

HYP0CLKP

AT10 I

AT9

I

HyperLink reference clock to drive HyperLink0 SerDes

HYP1CLKN

HYP1CLKP

AW5 I

AW4 I

HyperLink reference clock to drive HyperLink1 SerDes

LRESET

AE4

I

Up

Warm reset

LRESETNMIEN

AD4

I

Up

Enable for core selects

NMI

AD5

I

Up

Non-maskable interrupt

PACLKSEL

AN30 I

Down PA clock select to choose between core clock and PASSCLK pins

PASSCLKN

PASSCLKP

AV34 I

AV33 I

Packet Accelerator subsystem reference clock

PCIECLKN

PCIECLKP

AW32 I

AW31 I

PCIe clock input to drive PCIe SerDes

POR

AK4

I

Power-on reset

RESETFULL

AD3

I

Up

Full reset

RESET

AD2

I

Up

Warm reset of non isolated portion of the device

RESETSTAT

AC5

O Up

Reset status output

SRIOSGMIICLKN

SRIOSGMIICLKP

AW35 I

AW34 I

RapidIO/SGMII reference clock to drive the RapidIO and SGMII SerDes

SYSCLKN

SYSCLKP

AK3

I

AL3

I

System clock input to antenna interface and Main PLL (Main PLL optional vs. ALTCORECLK)

SYSCLKOUT

AK1

OZ Down System clock output to be used as a general purpose output clock for debug purposes

TSREFCLKN

TSREFCLKP

AL1

I

AM1

I

External precision clock source for SyncE

40 Terminals

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