TCI6636K2H Datasheet, PDF(39/362 Page) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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TCI6636K2H Datasheet, PDF (39/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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TCI6636K2H

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

SPRS835FâOctober 2013

Table 5-2

Terminal Functions â Signals and Control by Function (Part 2 of 19)

Signal Name

Ball No. Type IPD/IPU Description

AIFTXN0

AP17 O

AIFTXP0

AIFTXN1

AIFTXP1

AIFTXN2

AIFTXP2

AIFTXN3

AP18 O

AR16 O

AR17 O

AT15 O

AT16 O

AP14 O

Antenna Interface transmit data (6 links)

AIFTXP3

AP15 O

AIFTXN4

AR13 O

AIFTXP4

AR14 O

AIFTXN5

AT12 O

AIFTXP5

AIFREFRES0

AIFREFRES1

EXTFRAMEEVENT

PHYSYNC

RADSYNC

RP1CLKN

RP1CLKP

AT13 O

AM15 A

Antenna Interface SERDES0 reference resistor input (3 kÎ© +/- 1%)

AM11 A

Antenna Interface SERDES1 reference resistor input (3 kÎ© +/- 1%)

Antenna Timer

AC4

OZ Down Frame sync clock output

AP34 I

Down Alternate frame sync clock input (vs. FSYNCCLK(N|P)

AM30 I

Down Alternate frame sync input (vs. FRAMBURST (N|P)

AP2

I

AR2

I

Frame sync interface clock used to drive the frame synchronization interface (OBSAI RP1 clock)

RP1FBN

RP1FBP

AT1

I

AR1

I

Frame burst to drive frame indicators to the frame synchronization module (OBSAI RP1)

Boot Configuration Pins

ARMAVSSHAREDâ G24

I

Down Boot strapped pin to share ARM AVS with SoC. Pin shared with CORESEL3.

AVSIFSEL0â

AVSIFSEL1â

M2

I

Down Default value (Boot Strapped) for SR PINMUX register (SR_PINCTL). Pins shared with TIMI0 and

M1

I

Down TIMI1.

BOOTMODE_RSVDâ B31

I

Down Bootmode reserved pin. Pin shared with GPIO15.

BOOTMODE00â

B30

I

Down

BOOTMODE01â

D29

I

Down

BOOTMODE02â

A35

I

Down

BOOTMODE03â

B29

I

Down

BOOTMODE04â

E29

I

Down

BOOTMODE05â

BOOTMODE06â

BOOTMODE07â

D30

I

Down User defined Boot Mode pins

C30

I

Down See 8.1.2 ââBoot Modes Supportedââ on page 209 for more details.

A30

I

Down (â Pins are secondary functions and are shared with GPIO[01:13])

BOOTMODE08â

G30

I

Down

BOOTMODE09â

F31

I

Down

BOOTMODE10â

E30

I

Down

BOOTMODE11â

F30

I

Down

BOOTMODE12â

A31

I

Down

BOOTMODE13â

BOOTMODE14â

BOOTMODE15â

F24

I

E24

I

D24

I

User defined Boot Mode pins

See 8.1.2 ââBoot Modes Supportedââ on page 209 for more details.

(â Pins are secondary functions and are shared with CORESEL[0:2])

Copyright 2013 Texas Instruments Incorporated

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Terminals 39

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