TCI6636K2H Datasheet, PDF (97/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-6
Master ID Settings (Part 4 of 4)
Master ID
TCI6636K2H
157
CPT_RAC_FEI
158
CPT_RAC_CFG1
159
CPT_TAC_BE
160
CPT_QM_CFG2
161
CPT_DDR3B
162
CPT_RAC_CFG2
163
CPT_BCR_CFG
164
CPT_EDMA3CC0_4
165
CPT_EDMA3CC1_2_3
166
CPT_INTC
167
CPT_SPI_ROM_EMIF16
168
USB
169
EDMA4_TC0 read
170
EDMA4_TC0 write
171
EDMA4_TC1 read
172
EDMA4_TC1 write
173
EDMA4_CC_TR
174
CPT_MSMC5
175
CPT_MSMC6
176
CPT_MSMC7
177
CPT_MSMC4
178
Reserved
179
TAC FEI2
180-183
NETCP
184-255
End of Table 6-6
Reserved
1 The master ID for MSMC is for the transaction initiated by MSMC internally and sent to the DDR.
Note—There are two master ID values assigned to the Queue Manager_second master port, one master ID
for external linking RAM and the other one for the PDSP/MCDM accesses.
Table 6-7 shows the privilege ID of each C66x CorePac and every mastering peripheral. The table also shows the
privilege level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs.
data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being
executed at the time of the access or the configuration of the master peripheral.
Table 6-7
Privilege ID Settings (Part 1 of 2)
Privilege ID Master
0
C66x CorePac0
1
C66x CorePac1
2
C66x CorePac2
3
C66x CorePac3
4
C66x CorePac4
Privilege Level
SW dependent, driven by MSMC
SW dependent, driven by MSMC
SW dependent, driven by MSMC
SW dependent, driven by MSMC
SW dependent, driven by MSMC
Security Level
Non-secure
Non-secure
Non-secure
Non-secure
Non-secure
Access Type
DMA
DMA
DMA
DMA
DMA
Copyright 2013 Texas Instruments Incorporated
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Memory, Interrupts, and EDMA for TCI6636K2H 97