TCI6636K2H Datasheet, PDF (231/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.5 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for:
• Any level of customization to current boot methods
• Definition of a completely customized boot
8.1.3 SoC Security
The TI SoC contains security architecture that allows the C66x CorePacs and ARM CorePac to perform secure
accesses within the device. For more information, contact a TI sales office for additional information available with
the purchase of a secure device.
8.1.4 System PLL Settings
The PLL default settings are determined by the BOOTMODE[7:5] bits. Table 8-27 shows the settings for various
input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet
boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See
Table 8-11 for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip
divider to reduce the frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip
divider (/3), applies 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. The ARM CorePac PLL, DDR3A PLL,
DDR3B PLL and PASS PLL are controlled by chip level MMRs. For details on how to set up the PLL see Section
10.5 ‘‘Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers’’ on page 292.For details
on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User
Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
Table 8-27 System PLL Configuration
BOOTMODE
[7:5]
Input Clock
Freq (MHz)
800 MHz Device
1000 MHz Device
PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ
1200 MHz Device
PLLD PLLM DSP ƒ
0b000
50.00
0
31
800 0
39
1000 0
47
1200
0b001
66.67
0
23
800.04 0
29
1000.05 0
35
1200.06
0b010
80.00
0
19
800 0
24
1000 0
29
1200
0b011
100.00
0
15
800 0
19
1000 0
23
1200
0b100
156.25
3
40
800.78 4
63
1000 2
45
1197.92
0b101
250.00
4
31
800 0
7
1000 4
47
1200
0b110
312.50
7
40
800.78 4
31
1000 2
22
1197.92
0b111
122.88
End of Table 8-27
0
12
798.72 3
64
999.989 0
19
1228.80
1 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
2 ƒ represents frequency in MHz.
PA = 350 MHz ⁽¹⁾
PLLD PLLM DSP ƒ ⁽²⁾
0
41
1050
1
62
1050.053
3
104 1050
0
20
1050
24
335 1050
4
41
1050
24
167 1050
11
204 1049.6
8.1.4.1 ARM CorePac System PLL Settings
The PLL default settings are determined by the BOOTMODE[11:9] bits. Table 8-28 shows settings for various input
clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
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Device Boot and Configuration 231