TCI6636K2H Datasheet, PDF (222/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-14 HyperLink Boot Device Configuration Field Descriptions (Part 2 of 2)
Bit Field
Description
7-5 SYS PLL
Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
Default system reference clock is 156.25 MHz. Table 8-27 shows settings for various input clock frequencies.
4-1 Boot Devices Boot Devices[4:1]
1110 = HyperLink boot mode
Others = Other boot modes
0
Lendian
End of Table 8-14
Endianess
0 = Big endian
1 = Little endian
8.1.2.3.3 UART Boot Device Configuration
Figure 8-12 UART Boot Mode Configuration Field Description
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12
11 10 9
8
7
6
5
X X X X Port X
XX
Boot Master=1
Sys PLL Config
X X X X Port
ARM PLL Cfg
Boot Master=0
Sys PLL Config
4 321
Min
111
Min
111
0
Lendian
Lendian
Table 8-15 UART Boot Configuration Field Descriptions
Bit Field
Description
16-13 Reserved
Not Used
12
Port
UART Port number
0 = UART0
1 = UART1
11-9 ARM PLL Setting The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device.
Table 8-27 shows settings for various input clock frequencies.
8
Boot Master
Boot Master select
0 = ARM is boot master
1 = C66x is boot master
7-5 SYS PLL Setting The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
Table 8-27 shows settings for various input clock frequencies. (default = 4)
4
Min
Minimum boot configuration select bit.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for
configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1]
111 = UART boot mode
Others = Other boot modes
0
Lendian
End of Table 8-15
Endianess
0 = Big endian
1 = Little endian
222 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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