TCI6636K2H Datasheet, PDF (346/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-60 ICEPick Debug Secondary TAPs (Part 2 of 2)
Tap #
14
Type
CS
Name
IR Scan
Length
CS_DAP (APB-AP) 4
CS_DAP (AHB-AP)
End of Table 10-60
Access in
Secure Device Description
No
ARM A15 Cores (This is an internal TAP and not exposed at the DEBUGSS
boundary)
PDSP Cores (This is an internal TAP and not exposed at the DEBUGSS boundary)
For more information on ICEPick, see the Debug and Trace for KeyStoneII Devices in 2.4 ‘‘Related Documentation
from Texas Instruments’’ on page 19.
10.36 Debug Port (EMUx)
The device also supports 34 emulation pins— EMU[33:0], which includes 19 dedicated EMU pins and 15 pins
multiplexed with GPIO. These pins are shared by A15/DSP/STM trace, cross triggering, and debug bootmodes as
shown in Table 10-64. The 34-pin dedicated emulation interface is also defined in the following table.
Note—Note that if EMU[1:0] signals are shared for cross-triggering purposes in the board level, they
SHOULD NOT be used for trace purposes.
Table 10-61 Emulation Interface with Different Debug Port Configurations (Part 1 of 2)
Cross
EMU Pins Triggering
ARM Trace
DSP Trace
STM
EMU33
TRCDTa[29] TRCDTb[31]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU32
TRCDTa[28] TRCDTb[30]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU31
TRCDTa[27] TRCDTb[29]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU30
TRCDTa[26] TRCDTb[28]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU29
TRCDTa[25] TRCDTb[27]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU28
TRCDTa[24] TRCDTb[26]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU27
TRCDTa[23] TRCDTb[25]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU26
TRCDTa[22] TRCDTb[24]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU25
TRCDTa[21] TRCDTb[23]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU24
TRCDTa[20] TRCDTb[22]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU23
TRCDTa[19] TRCDTb[21] TRCDTa[19]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU22
TRCDTa[18] TRCDTb[20] TRCDTa[18]
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU21
TRCDTa[17] TRCDTb[19] TRCDTa[17] TRCDTb[19] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU20
TRCDTa[16] TRCDTb[18] TRCDTa[16] TRCDTb[18] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU19
TRCDTa[15] TRCDTb[17] TRCDTa[15] TRCDTb[17] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
Debug
Boot Mode
346 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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