TCI6636K2H Datasheet, PDF (344/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.35.1.1 ARM Subsystem Features
– Support for invasive debug like halt mode debugging (breakpoint, watchpoints) and monitor mode
debugging
– Support for non-invasive debugging (program trace, performance monitoring)
– Support for A15 Performance Monitoring Unit (cycle counters)
– Support for per core CoreSight^ Program Trace Module (CS-PTM) with timing
– Support for an integrated CoreSight System Trace Module (CS-STM) for hardware event and software
instrumentation
– A shared timestamp counter for all ARM cores and STM is integrated in ARMSS for trace data correlation
– Support for a 16KB Trace Buffer and Router (TBR) to hold PTM/STM trace. The trace data is copied by
EDMA to external memory for draining by device high speed serial interfaces.
– Support for simultaneous draining of trace stream through EMUn pins and TBR (to achieve higher
aggregate trace throughput)
– Support for debug authentication interface to disable debug accesses in secure devices
– Support for cross triggering between MPU cores, CS-STM and CT-TBR
– Support for debug through warm reset
10.35.1.2 DSP Features
– Support for Halt-mode debug
– Support for Real-time debug
– Support for Monitor mode debug
– Advanced Event Triggering (AET) for data/PC watch-points, event monitoring and visibility into external
events
– Support for PC/Timing/Data/Event trace.
– TETB (TI Embedded Trace Buffer) of 4KB to store PC/Timing/Data/Event trace. The trace data is copied
by EDMA to external memory for draining by device high speed serial interfaces or it can be drained
through EMUx pins
– Support for Cross triggering source/sink to other C66x CorePacs and device subsystems.
– Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
– Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report
For more information on the AET, see the following documents in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19:
10.35.2 ICEPick Module
The debugger is connected to the device through its external JTAG interface. The first level of debug interface seen
by the debugger is connected to the ICEPick module embedded in the DEBUGSS. ICEPick is the chip-level TAP,
responsible for providing access to the IEEE 1149.1 and IEEE1149.6 boundary scan capabilities of the device.
The device has multiple processors, some with secondary JTAG TAPs (C66x CorePacs) and others with an APB
memory mapped interface (ARM CorePac and Coresight components). ICEPick manages the TAPs as well as the
power/reset/clock controls for the logic associated with the TAPs as well as the logic associated with the APB ports.
ICEPick provides the following debug capabilities:
• Debug connect logic for enabling or disabling most ICEPick instructions
344 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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