TCI6636K2H Datasheet, PDF (241/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register clears the status of LRESET and NMI based on CORESEL[2:0]. The
LRESETNMI PIN Status Clear Register is shown in the figure and table below.
Figure 8-17 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
NMI7 NMI6 NMI5 NMI4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
R-0
WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0 WC-0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Table 8-35 LRESETNMI PIN Status Clear Register Field Descriptions
Bit Field
31-16 Reserved
15 NMI7
14 NM6
13 NMI5
12 NMI4
11 NMI3
10 NMI2
9
NMI1
8
NMI0
7
LR7
6
LR6
5
LR5
4
LR4
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 8-35
Description
Reserved
C66x CorePac7 in NMI Clear
C66x CorePac6 in NMI Clear
C66x CorePac5 in NMI Clear
C66x CorePac4 in NMI Clear
C66x CorePac3 in NMI Clear
C66x CorePac2 in NMI Clear
C66x CorePac1 in NMI Clear
C66x CorePac0 in NMI Clear
C66x CorePac7 in Local Reset Clear
C66x CorePac6 in Local Reset Clear
C66x CorePac5 in Local Reset Clear
C66x CorePac4 in Local Reset Clear
C66x CorePac3 in Local Reset Clear
C66x CorePac2 in Local Reset Clear
C66x CorePac1 in Local Reset Clear
C66x CorePac0 in Local Reset Clear
8.2.3.7 Reset Status (RESET_STAT) Register
The Reset Status Register (RESET_STAT) captures the status of local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps.
• In case of local reset: The LRx bits are written as 1 and the GR bit is written as 0 only when the C66x CorePac
receives a local reset without receiving a global reset.
• In case of global reset: The LRx bits are written as 0 and the GR bit is written as 1 only when a global reset is
asserted.
Copyright 2013 Texas Instruments Incorporated
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Device Boot and Configuration 241