TCI6636K2H Datasheet, PDF (263/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-59 USB_PHY_CTL3 Register Field Descriptions (Part 2 of 2)
Bit
Field
Description
16-11 Reserved
Reserved
10-5 PHY_PC_PCS_TX_DEEMPH_3P5DB Tx De-Emphasis at 3.5 dB.
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3
specification). Can be used for Rx eye compliance.
4-0
PHY_PC_LOS_LEVEL
Loss-of-Signal Detector Sensitivity Level Control.
Sets the LOS detection threshold level. This signal must be set to 0x9.
End of Table 8-59
Figure 8-42 USB_PHY_CTL4 Register
31
30
PHY_SSC_EN
PHY_REF_USE_PAD
R/W-1
R/W-0
29
PHY_REF_SSP_EN
R/W-0
28
PHY_MPLL_REFSSC_CLK_EN
R/W-0
27
22
PHY_FSEL
R/W-100111
21
PHY_RETENABLEN
R/W-1
20
19
PHY_REFCLKSEL
R/W-10
18
PHY_COMMONONN
R/W-0
17
Reserved
R-0
16
15
14
12
11
7
PHY_OTG_VBUSVLDEXTSEL
PHY_OTG_OTGDISABLE PHY_PC_TX_VBOOST_LVL PHY_PC_LANE0_TX_TERM_OFFSET
R/W-0
R/W-1
R/W-100
R/W-00000
Legend: R = Read only; R/W = Read/Write, -n = value after reset
6
0
Reserved
R-0
Table 8-60 USB_PHY_CTL4 Register Field Descriptions (Part 1 of 2)
Bit
Field
31
PHY_SSC_EN
30
PHY_REF_USE_PAD
29
PHY_REF_SSP_EN
28
PHY_MPLL_REFSSC_CLK_EN
27-22 PHY_FSEL
21
PHY_RETENABLEN
Description
Spread Spectrum Enable.
Enables spread spectrum clock production (0.5% down-spread at ~31.5 KHz) in the USB3.0 PHY. If the
reference clock already has spread spectrum applied, ssc_en must be de-asserted.
Select Reference Clock Connected to ref_pad_clk_{p,m}.
When asserted, selects the external ref_pad_clk_{p,m} inputs as the reference clock source. When
de-asserted, ref_alt_clk_{p,m} are selected for an on-chip reference clock source.
Reference Clock Enables for SS function.
Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de asserted until the
reference clock is running at the appropriate frequency, at which point ref_ssp_en can be asserted. For
lower power states, ref_ssp_en can also be de asserted.
Double-Word Clock Enable.
Enables/disables the mpll_refssc_clk signal. To prevent clock glitch, it must be changed when the PHY
is inactive.
Frequency Selection.
Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined
with the other clock and enable signals will determine the clock frequency used for SS and HS
operations and if a shared or separate reference clock will be used.
Lowered Digital Supply Indicator.
Indicates that the vp digital power supply has been lowered in Suspend mode. This signal must be
de-asserted before the digital power supply is lowered.
1 = Normal operating mode.
0 = The analog blocks are powered down.
Copyright 2013 Texas Instruments Incorporated
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