TCI6636K2H Datasheet, PDF (16/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 2-1
Characteristics of the TCI6636K2H Processor (Part 2 of 2)
HARDWARE FEATURES
TCI6636K2H
JTAG BSDL_ID
JTAGID Register (address location: 0x02620018)
0x0b98102f (PG 1.0)
0x1b98102f (PG 1.1)
Frequency
C66x
ARM Cortex-A15
Up to 1.2 GHz
Up to 1.4 GHz
Voltage
Core (V)
I/O (V)
SmartReflex variable supply
0.85 V, 1.0 V, 1.35 V, 1.5 V, 1.8 V, and 3.3 V
BGA Package
Process Technology
40 mm × 40 mm
μm
AAW 1517-pin flip-chip plastic BGA
0.028 μm
Product Status ⁽³⁾
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
PD
End of Table 2-1
1 The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details
2 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
3 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
2.1 C66x DSP CorePac
The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements and new
features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs
support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the
vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute
instructions that operate on 128-bit vectors. The C66x CPU also supports SIMD for floating-point operations.
Improved vector processing capability (each instruction can process multiple data in parallel) combined with the
natural instruction level parallelism of C6000 architecture (e.g., execution of up to 8 instructions per cycle) results
in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized
C/C++ compiler.
Each C66x DSP CorePac has two Rake and Search Accelerators (RSA) integrated on-chip. The tightly coupled
accelerator RSA can be used for:
• Chip rate spreading of WCDMA Rel’99, CDMA2000, HSDPA, and HSDPA+
• Chip rate despreading and correlation of WCDMA Rel’99, HSDPA, and HSDPA+ (e.g., Rake receiver,
preamble detection)
• Reed-Muller decoding
For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following
documents (2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19):
• C66x CPU and Instruction Set Reference Guide
• C66x DSP Cache User Guide
• C66x CorePac User Guide
16 Device Characteristics
Copyright 2013 Texas Instruments Incorporated
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