TCI6636K2H Datasheet, PDF (321/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Figure 10-36 I²C Transmit Timings
26
SDA
23
SCL
19
25
16
18
TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
24
21
20
28
27
22
18
17
Stop
Start
Repeated
Start
Stop
10.11 SPI Peripheral
The Serial Peripheral Interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot. The SPI module on
TCI6636K2H is supported only in master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
10.11.1 SPI Electrical Data/Timing
Table 10-41 SPI Timing Requirements
See Figure 10-37)
No.
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0
7 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0
8 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
End of Table 10-41
Min Max Unit
2
ns
2
ns
2
ns
2
ns
5
ns
5
ns
5
ns
5
ns
Table 10-42 SPI Switching Characteristics (Part 1 of 2)
(See Figure 10-37 and Figure 10-38)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1 tc(SPC)
Cycle time, SPICLK, all master modes
3*P2 ⁽¹⁾
ns
2 tw(SPCH)
Pulse width high, SPICLK, all master modes
0.5*(3*P2) - 1
ns
3 tw(SPCL)
Pulse width low, SPICLK, all master modes
0.5*(3*P2) - 1
ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 0.
5
ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 1.
5
ns
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 0
5
ns
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
TCI6636K2H Peripheral Information and Electrical Specifications 321