TCI6636K2H Datasheet, PDF (108/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
6.3 Interrupts
This section discusses the interrupt sources, controller, and topology. Also provided are tables describing the
interrupt events.
6.3.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the TCI6636K2H device are configured through the C66x CorePac Interrupt Controller. The
Interrupt Controller allows for up to 128 system events to be programmed to any of the 12 CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In addition, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through the CorePac Interrupt Controller blocks, CIC[2:0]. This is clocked
using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, ARM
GIC (ARM Generic Interrupt Controller) plus the EDMA3CC. CIC0 has 104 event outputs which provides 20
broadcast events and 18 additional events to each of the C66x CorePacs, 0 through 3. Similarly, CIC1 has 104 event
outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 4 through 7.
CIC2 has 103 event outputs which provides 8, 20, 8, 8, 8, and 16 events to EDMA3CC0, EDMA3CC1, EDMA3C2,
EDMA3CC3, EDMA3CC4, and HyperLinks respectively.
The events that are routed to the C66x CorePacs for Advanced Event Triggering (AET) purposes from those
EDMA3CC and FSYNC events that are not otherwise provided to each C66x CorePac.
Modules such as FFTC, TCP3d, TAC, AIF, CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI
handshaking interface. The EOI value is 0 for TCP3d_x, TAC, AIF, CP_MPU, BOOT_CFG, and CP_Tracer.
For FFTC:
– the EOI value is 0 for FFTC_x_INTD_INTR0,
– the EOI value is 1 for FFTC_x_INTD_INTR1,
– the EOI value is 2 for FFTC_x_INTD_INTR2
– the EOI value is 3 for FFTC_x_INTD_INTR3 (where FFTC_x can be FFTC_0, FFTC_1, FFTC_2 or
FFTC_3)
108 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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