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| TCI6636K2H Datasheet, PDF (339/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC) | |||
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TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835FâOctober 2013
Table 10-59 EMIF16 Asynchronous Memory Timing Requirements (1) (Part 2 of 2)
(see Figure 10-58 through Figure 10-61)
No.
Min
Max
Unit
Read Timing
3
tC(CEL)
EMIF read cycle time when ew = 0, meaning not in extended wait mode
(RS+RST+RH+3) (RS+RST+RH+3) ns
*E-3
*E+3
3
tC(CEL)
EMIF read cycle time when ew =1, meaning extended wait mode enabled
(RS+RST+RH+3) (RS+RST+RH+3) ns
*E-3
*E+3
4
tosu(CEL-OEL) Output setup time from CE low to OE low. SS = 0, not in select strobe mode
(RS+1) * E - 3 (RS+1) * E + 3 ns
5
toh(OEH-CEH) Output hold time from OE high to CE high. SS = 0, not in select strobe mode
(RH+1) * E - 3 (RH+1) * E + 3 ns
4
tosu(CEL-OEL) Output setup time from CE low to OE low in select strobe mode, SS = 1
(RS+1) * E - 3 (RS+1) * E + 3 ns
5
toh(OEH-CEH) Output hold time from OE high to CE high in select strobe mode, SS = 1
(RH+1) * E - 3 (RH+1) * E + 3 ns
6
tosu(BAV-OEL) Output setup time from BA valid to OE low
(RS+1) * E - 3 (RS+1) * E + 3 ns
7
toh(OEH-BAIV) Output hold time from OE high to BA invalid
(RH+1) * E - 3 (RH+1) * E + 3 ns
8
tosu(AV-OEL)
Output setup time from A valid to OE low
(RS+1) * E - 3 (RS+1) * E + 3 ns
9
toh(OEH-AIV)
Output hold time from OE high to A invalid
(RH+1) * E - 3 (RH+1) * E + 3 ns
10 tw(OEL)
OE active time low, when ew = 0. Extended wait mode is disabled.
(RST+1) * E - 3 (RST+1) * E + 3 ns
10 tw(OEL)
OE active time low, when ew = 1. Extended wait mode is enabled.
(RST+1) * E - 3 (RST+1) * E + 3 ns
11 td(WAITH-OEH) Delay time from WAIT deasserted to OE# high
4E + 3 ns
12 tsu(D-OEH)
Input setup time from D valid to OE high
3
ns
13 th(OEH-D)
Input hold time from OE high to D invalid
0.5
ns
Write Timing
15
tc(CEL)
EMIF write cycle time when ew = 0, meaning not in extended wait mode
(WS+WST+WH+ (WS+WST+WH+ ns
TA+4)*E-3
TA+4)*E+3
15
tc(CEL)
EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WH+ (WS+WST+WH+ ns
TA+4)*E-3
TA+4)*E+3
16 tosuCEL-WEL)
17 toh(WEH-CEH)
16 tosuCEL-WEL)
17 toh(WEH-CEH)
18 tosu(RNW-WEL)
19 toh(WEH-RNW)
20 tosu(BAV-WEL)
21 toh(WEH-BAIV)
22 tosu(AV-WEL)
23 toh(WEH-AIV)
24 tw(WEL)
24 tw(WEL)
26 tosu(DV-WEL)
27 toh(WEH-DIV)
25 td(WAITH-WEH)
End of Table 10-59
Output setup time from CE low to WE low. SS = 0, not in select strobe mode
Output hold time from WE high to CE high. SS = 0, not in select strobe mode
Output setup time from CE low to WE low in select strobe mode, SS = 1
Output hold time from WE high to CE high in select strobe mode, SS = 1
Output setup time from RNW valid to WE low
Output hold time from WE high to RNW invalid
Output setup time from BA valid to WE low
Output hold time from WE high to BA invalid
Output setup time from A valid to WE low
Output hold time from WE high to A invalid
WE active time low, when ew = 0. Extended wait mode is disabled.
WE active time low, when ew = 1. Extended wait mode is enabled.
Output setup time from D valid to WE low
Output hold time from WE high to D invalid
Delay time from WAIT deasserted to WE# high
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WST+1) * E - 3
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4E + 3 ns
1 E = 1/(SYSCLK1/6)
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 339
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