TCI6636K2H Datasheet, PDF (54/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 5-2
Signal Name
SGMII3TXN
SGMII3TXP
SGMIIREFRES
VCL
VCNTL0
VCNTL1
VCNTL2
VCNTL3
VCNTL4
VCNTL5
VD
SPI0CLK
SPI0DIN
SPI0DOUT
SPI0SCS0
SPI0SCS1
SPI0SCS2
SPI0SCS3
SPI1CLK
SPI1DIN
SPI1DOUT
SPI1SCS0
SPI1SCS1
SPI1SCS2
SPI1SCS3
SPI2CLK
SPI2DIN
SPI2DOUT
SPI2SCS0
SPI2SCS1
SPI2SCS2
SPI2SCS3
TSCOMPOUT
TSPUSHEVT0
TSPUSHEVT1
TSSYNCEVT
TIMI0
TIMI1
Terminal Functions — Signals and Control by Function (Part 17 of 19)
Ball No. Type IPD/IPU Description
AP25 O
AP26 O
AM24 A
Ethernet MAC SGMII port 3 transmit data
SGMII SerDes reference resistor input (3 kΩ +/- 1%)
AP36 IOZ
SmartReflex
Voltage control I²C clock
AT39 OZ
AR37 OZ
AR36 OZ
AT38 OZ
Voltage control outputs to variable core power supply
AU38 OZ
AR35 OZ
AP35 IOZ
Voltage control I²C data
SPI0
B26
OZ Down SPI0 clock
A26
I
Down SPI0 data in
A27
OZ Down SPI0 data out
F25
OZ Up
SPI0 interface enable 0
C25
OZ Up
SPI0 interface enable 1
E26
OZ Up
SPI0 interface enable 2
D26
OZ Up
SPI0 interface enable 3
SPI1
C28
OZ Down SPI1 clock
F27
I
Down SPI1 data in
A28
OZ Down SPI1 data out
B27
OZ Up
SPI1 interface enable 0
C27
OZ Up
SPI1 interface enable 1
D27
OZ Up
SPI1 interface enable 2
E27
OZ Up
SPI1 interface enable 3
SPI2
D25
OZ Down SPI2 clock
F28
I
Down SPI2 data in
G28
OZ Down SPI2 data out
B28
OZ Up
SPI2 interface enable 0
D28
OZ Up
SPI2 interface enable 1
A29
OZ Up
SPI2 interface enable 2
E25
OZ Up
SPI2 interface enable 3
Sync-Ethernet / IEEE1588
AB1
O Down IEEE1588 compare output.
AC2
IOZ Down PPS push event from GPS for IEEE1588
AC1
IOZ Down Push event from BCN for IEEE1588
AC3
O Down IEEE1588 sync event output.
Timer
M2
I
Down
Timer inputs
M1
I
Down
54 Terminals
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