TCI6636K2H Datasheet, PDF (253/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.18 Reset Mux (RSTMUXx) Register
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX11
for each of the C66x CorePacs and ARM CorePac on the device. These registers are located in Bootcfg memory
space. The Reset Mux Register is shown in the figure and table below.
Figure 8-29 Reset Mux Register
31
10
9
8
7
5
Reserved
EVTSTATCLR
Reserved
DELAY
R-0000 0000 0000 0000 0000 00
RC-0
R-0
RW-100
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
4
EVTSTAT
R-0
3
1
OMODE
RW-000
0
LOCK
RW-0
Table 8-47 Reset Mux Register Field Descriptions
Bit
31-10
9
Field
Reserved
EVTSTATCLR
8
Reserved
7-5 DELAY
4
EVTSTAT
3-1 OMODE
0
LOCK
End of Table 8-47
Description
Reserved
Clear event status
0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
Delay cycles between NMI & local reset
000b = 256 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
010b = 1024 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
011b = 2048 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
100b = 4096 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b (default)
101b = 8192 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
110b = 16384 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
111b = 32768 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
Event status
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
Timer event operation mode
000b = WD timer event input to the Reset Mux block does not cause any output event (default)
001b = Reserved
010b = WD Timer Event input to the Reset Mux block causes local reset input to C66x CorePac. Note that for Cortex-A15
processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset
generation to generate reset to PLL Controller.
011b = WD Timer Event input to the Reset Mux block causes NMI input to C66x CorePac. Note that for Cortex-A15 processor
watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to
generate reset to PLL Controller.
100b = WD Timer Event input to the Reset Mux block causes NMI input followed by local reset input to C66x CorePac. Delay
between NMI and local reset is set in DELAY bit field. Note that for Cortex-A15 processor watchdog timers, the Local Reset
output event of the RSTMUX logic is connected to the Device Reset generation to generate reset to PLL Controller.
101b = WD timer event input to the Reset Mux block causes device reset to TCI6636K2H. Note that for Cortex-A15 processor
watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to
generate reset to PLL Controller.
110b = Reserved
111b = Reserved
Lock register fields
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
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Device Boot and Configuration 253