TCI6636K2H Datasheet, PDF (237/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-30 Device State Control Registers (Part 4 of 4)
Address Start
0x02620338
0x02620350
0x02620354
0x02620358
0x0262035C
0x02620360
0x02620364
0x02620368
0x0262036C
0x02620370
0x02620374
0x02620378
0x0262039C
0x02620400
0x02620404
0x02620408
0x0262040C
0x02620600
0x02620700
Address End
0x0262034F
0x02620353
0x02620357
0x0262035B
0x0262035F
0x02620363
0x02620367
0x0262036B
0x0262036F
0x02620373
0x02620377
0x0262039B
0x0262039F
0x02620403
0x02620407
0x0262040B
0x026205FF
0x026206FF
0x02620703
Size
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
132B
4B
4B
4B
4B
62B
256B
4B
Acronym
Reserved
MAINPLLCTL0
MAINPLLCTL1
PASSPLLCTL0
PASSPLLCTL1
DDR3APLLCTL0
DDR3APLLCTL1
DDR3BPLLCTL0
DDR3BPLLCTL1
ARMPLLCTL0
ARMPLLCTL1
Reserved
Reserved
ARMENDIAN_CFG0_0
ARMENDIAN_CFG0_1
ARMENDIAN_CFG0_2
Reserved
Reserved
CHIP_MISC_CTL0
0x02620704
0x02620710
0x0262070F
0x02620713
12B Reserved
4B SYSENDSTAT
0x02620714
0x02620718
0x0262071C
0x02620720
0x02620730
0x02620734
0x02620738
0x02620717
0x0262071B
0x0262071F
0x0262072F
0x02620733
0x02620737
0x0262074F
4B Reserved
4B Reserved
4B Reserved
16B Reserved
4B SYNCECLK_PINCTL
4B Reserved
24B USB_PHY_CTL
0x02620750
0x02620800
0x02620C7C
0x026207FF
0x02620C7B
0x02620C7F
176B Reserved
1148B Reserved
4B CHIP_MISC_CTL1
0x02620C80
0x02620C97
0x02620C98
0x02620C9B
0x02620C9C
0x02620FFF
End of Table 8-30
24B
4B
868B
Reserved
DEVSPEED
Reserved
Description
See section 10.5 ‘‘Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL,
PASS PLL and the PLL Controllers’’ on page 292
See section 10.7 ‘‘PASS PLL’’ on page 311
See section 10.6 ‘‘DDR3A PLL and DDR3B PLL’’ on page 309
See section 10.6 ‘‘DDR3A PLL and DDR3B PLL’’ on page 309
See section ‘‘ARM CorePac System PLL Settings’’ on page 231
See section ‘‘ARM Endian Configuration Register 0
(ARMENDIAN_CFGr_0), r=0..7’’ on page 255
See section ‘‘Chip Miscellaneous Control (CHIP_MISC_CTL0)
Register’’ on page 256
See section ‘‘System Endian Status Register (SYSENDSTAT)’’ on
page 257
See section ‘‘SYNECLK_PINCTL Register’’ on page 258
See section ‘‘USB PHY Control (USB_PHY_CTLx) Registers’’ on
page 258
See section ‘‘Chip Miscellaneous Control (CHIP_MISC_CTL1)
Register’’ on page 257
See section ‘‘Device Speed (DEVSPEED) Register’’ on page 254
Copyright 2013 Texas Instruments Incorporated
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