TCI6636K2H Datasheet, PDF (9/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

List of Figures
TCI6636K2H
SPRS835F—February 2012—Revised October 2013
Figure 1-1
Figure 2-1
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 4-1
Figure 4-2
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Functional Block Diagram . . . . . . . . . . . . . . . . . . . .4
C66x™ DSP Device Nomenclature (including the
TCI6636K2H DSP). . . . . . . . . . . . . . . . . . . . . . . . . . . 18
C66x CorePac Block Diagram . . . . . . . . . . . . . . . 21
L1P Memory Configurations . . . . . . . . . . . . . . . . 22
L1D Memory Configurations . . . . . . . . . . . . . . . . 23
L2 Memory Configurations . . . . . . . . . . . . . . . . . 24
CorePac Revision ID Register (MM_REVID) . . . 27
KeyStone II ARM CorePac Block Diagram . . . . 28
ARM Interrupt Controller for Four Cortex-A15
Processor Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AAW 1517-PIN BGA Package (Bottom View) . 33
Pin Map Panels (Bottom View) . . . . . . . . . . . . . . 33
TCI6636K2K Pin Map Left Side Panel (A) —
Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TCI6636K2K Pin Map Left Center Panel (B) —
Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TCI6636K2K Pin Map Right Center Panel (C) —
Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TCI6636K2K Pin Map Right Side Panel (D) —
Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Configuration Register (CONFIG) . . . . . . . . . . . 100
Programmable Range n Start Address Register
(PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Programmable Range n End Address Register
(PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programmable Range n Memory Protection
Page Attribute Register (PROGn_MPPAR). . . 104
Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . 109
TeraNet 3_A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
TeraNet 3_A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
TeraNet 3_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
TeraNet C66x to SDMA . . . . . . . . . . . . . . . . . . . . 190
TeraNet 3P_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
TeraNet 3P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
TeraNet 6P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
TeraNet 3P_Tracer. . . . . . . . . . . . . . . . . . . . . . . . . 199
DEVSTAT Boot Mode Pins ROM Mapping . . . 210
Sleep Boot Mode Configuration Fields . . . . . 212
I²C Passive Mode Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
I²C Master Mode Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
SPI Device Configuration Fields . . . . . . . . . . . . 214
EMIF Boot Device Configuration Fields . . . . . 215
NAND Boot Device Configuration Fields. . . . 216
Serial Rapid I/O Boot Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Ethernet (SGMII) Boot Device Configuration
Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
PCIe Boot Device Configuration Fields . . . . . 220
HyperLink Boot Device Configuration Fields 221
UART Boot Mode Configuration Field
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Figure 8-20
Figure 8-21
Figure 8-22
Figure 8-23
Figure 8-24
Figure 8-25
Figure 8-26
Figure 8-27
Figure 8-28
Figure 8-29
Figure 8-30
Figure 8-31
Figure 8-32
Figure 8-33
Figure 8-34
Figure 8-35
Figure 8-36
Figure 8-37
Figure 8-38
Figure 8-39
Figure 8-40
Figure 8-41
Figure 8-42
Figure 8-43
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
Figure 10-7
Figure 10-8
Figure 10-9
Figure 10-10
Figure 10-11
Device Status Register. . . . . . . . . . . . . . . . . . . . . .238
Device Configuration Register (DEVCFG) . . . .239
JTAG ID (JTAGID) Register . . . . . . . . . . . . . . . . . .239
LRESETNMI PIN Status Register
(LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . .240
LRESETNMI PIN Status Clear Register
(LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . .241
Reset Status Register (RESET_STAT) . . . . . . . . .242
Reset Status Clear Register
(RESET_STAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . .243
Boot Complete Register (BOOTCOMPLETE). .243
Power State Control Register
(PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
NMI Generation Register (NMIGRx) . . . . . . . . .246
IPC Generation Registers (IPCGRx) . . . . . . . . . .246
IPC Acknowledgement Registers (IPCARx) . .247
IPC Generation Registers (IPCGRH) . . . . . . . . . .248
IPC Acknowledgement Register (IPCARH) . . .248
Timer Input Selection Register (TINPSEL) . . . .249
Timer Output Selection Register
(TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Reset Mux Register . . . . . . . . . . . . . . . . . . . . . . . . .253
Device Speed Register (DEVSPEED) . . . . . . . . .254
ARM Endian Configuration Register 0
(ARMENDIAN_CFGr_0), r=0..7. . . . . . . . . . . . . . .255
ARM Endian Configuration Register 1
(ARMENDIAN_CFGr_1), r=0..7. . . . . . . . . . . . . . .255
ARM Endian Configuration Register 2
(ARMENDIAN_CFGr_2), r=0..7. . . . . . . . . . . . . . .256
Chip Miscellaneous Control Register
(CHIP_MISC_CTL0) . . . . . . . . . . . . . . . . . . . . . . . . .256
Chip Miscellaneous Control Register
(CHIP_MISC_CTL1) . . . . . . . . . . . . . . . . . . . . . . . . .257
System Endian Status Register . . . . . . . . . . . . . .257
SYNECLK_PINCTL Register. . . . . . . . . . . . . . . . . .258
USB_PHY_CTL0 Register. . . . . . . . . . . . . . . . . . . .258
USB_PHY_CTL1 Register. . . . . . . . . . . . . . . . . . . .260
USB_PHY_CTL2 Register. . . . . . . . . . . . . . . . . . . .261
USB_PHY_CTL3 Register. . . . . . . . . . . . . . . . . . . .262
USB_PHY_CTL4 Register. . . . . . . . . . . . . . . . . . . .263
USB_PHY_CTL5 Register. . . . . . . . . . . . . . . . . . . .264
Core Before IO Power Sequencing . . . . . . . . . .274
IO-Before-Core Power Sequencing. . . . . . . . . .276
SmartReflex 4-Pin 6-bit VID Interface Timing279
RESETFULL Reset Timing . . . . . . . . . . . . . . . . . . .291
Soft/Hard Reset Timing. . . . . . . . . . . . . . . . . . . . .291
Boot Configuration Timing . . . . . . . . . . . . . . . . .292
Main PLL and PLL Controller . . . . . . . . . . . . . . . .293
PLL Secondary Control Register (SECCTL) . . .298
PLL Controller Divider Register (PLLDIVn) . . .298
PLL Controller Clock Align Control Register
(ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
PLLDIV Divider Ratio Change Status Register
(DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.