TCI6636K2H Datasheet, PDF (232/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
The ARM CorePac PLL is controlled using a PLL controller and a chip-level MMR. For details on how to set up the
PLL see Section 10.5 ‘‘Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers’’ on
page 292. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller for
KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
Table 8-28 ARM PLL Configuration
BOOTMODE Input Clock
[11:9]
Freq (MHz)
0b000
50.00
0b001
66.67
0b010
80.00
0b011
100.00
0b100
156.25
0b101
250.00
0b110
312.50
0b111
122.88
End of Table 8-28
800 MHz Device
PLLD PLLM DSP ƒ
0
31
800
0
23
800.04
0
19
800
0
15
800
0
40
800.78
4
31
800
7
40
800.78
0
12
798.72
1000 MHz Device
PLLD PLLM DSP ƒ
0
39
1000
0
29
1000.05
0
24
1000
0
19
1000
4
63
1000
0
7
1000
4
31
1000
3
64
999.40
1200 MHz Device
PLLD PLLM DSP ƒ
0
47
1200
0
35
1200.06
0
29
1200
0
23
1200
24 45
1197.92
4
47
1200
2
22
1197.92
0
19
1200.80
1400 MHz Device
PLLD PLLM DSP ƒ
0
55
1400
0
41
1400.07
0
34
1400
0
27
1400
0
17
1406.25
4
55
1400
0
8
1406.25
0
22
1413.12
232 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback