TCI6636K2H Datasheet, PDF (304/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions (Part 2 of 2)
Bit
Field
Description
11-6 Reserved
Reserved
5-0 PLLD
End of Table 10-25
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
Figure 10-18 Main PLL Control Register 1 (MAINPLLCTL1)
31
Reserved
RW - 0000000000000000000000000
Legend: RW = Read/Write; -n = value after reset
7
6
5
4
ENSAT
Reserved
RW-0
R-00
3
0
BWADJ[11:8]
RW- 0000
Table 10-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
Bit
Field
Description
31-7 Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper PLL operation
5-4 Reserved
Reserved
3-0 BWADJ[11:8]
End of Table 10-26
BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
10.5.4 ARM PLL Control Registers
The ARM PLL uses two chip-level registers (ARMPLLCTL0 and ARMPLLCTL1) without using the Main PLL
Controller like other PLLs for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg
space. To write to these registers, software must go through an un-locking sequence using the KICK0 and KICK1
registers. These registers reset only on a POR reset.
For valid configurable values of the ARMPLLCTL registers, see Section 8.1.4.1 ‘‘ARM CorePac System PLL
Settings’’ on page 231. See Section 8.2.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 240 for the
address location of the KICK registers and their locking and unlocking sequences.
See Figure 10-19 and Table 10-27 for ARMPLLCTL0 details and Figure 10-20 and Table 10-28 for ARMPLLCTL1
details.
.
Figure 10-19
ARM PLL Control Register 0 (ARMPLLCTL0) ⁽¹⁾
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
BYPASS
CLKOD
PLLM
PLLD
RW-0000 1001
RW-1
RW-0001
RW-0000000010011
RW-000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19.
304 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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