TCI6636K2H Datasheet, PDF (218/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-10 Serial Rapid I/O Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Lane
When Boot Master =0 (ARM is Boot Master), Pin[16] is used as Lane.
0 = 4 ports, each 1 lane wide (default)
1 = 2 ports, each 2lanes wide
When Boot Master =1 (C66x is Boot Master), Pin[16] is reserved.
15-14 Ref Clock
SRIO Reference clock frequency
0 = 125MHz
1 = 156.25MHz (default)
2 = Reserved
3 = Reserved
13-12 Data Rate
SRIO Data Rate
0 = 1.25 GBs
1 = 2.5 GBs
2 = 3.125 GBs
3 = 5 GBs (default)
11-9 Lane Setup/ARM PLL
Setting
When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting with all lanes enabled. The PLL
default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the
device. The default value is 156.26 Mhz. Table 8-27 shows settings for various input clock frequencies.
When Boot Master =1 (C66x is Boot Master), pin [11:9] are used as Lane Set up.
0 = 4 ports, each 1 lane wide (default)
1 = 3 ports, lanes 0, 1 form a 2 lane port, lane 2,3 are single ports
2 = 3 ports, lanes 0, 1 are single lane ports, lanes 2,3 form a 2 lane port
3 = 2 ports, lane 0, 1 are one port, lane 2, 3 are a second port
4 = 1 port, 4 lanes wide
5 - 7 = 4 ports, each 1 lane wide
8
Boot Master
Boot Master select
0 = ARM is boot master (default)
1 = C66x is boot master
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the
device. Default system reference clock is 156.25 MHz. Table 8-27 shows settings for various input clock
frequencies. (default = 4)
4
Min
Minimum boot configuration select bit.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1
Boot Devices
Boot Devices
100 = SRIO boot mode
Others = Other boot modes
0
Lendian
End of Table 8-10
Endianess
0 = Big endian
1 = Little endian
In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory
reserved for received messages is required and reception of messages cannot be prevented, the master can disable
the message mode by writing to the boot table and generating a boot restart.
218 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback