TCI6636K2H Datasheet, PDF (311/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
As shown in Figure 10-25, the output of DDR3A PLL and DDR3B PLL (PLLOUT) is divided by 2 and directly fed
to the DDR3A and DDR3B memory controller. During power-on resets, the internal clocks of the DDR3 PLL are
affected as described in Section 10.4 ‘‘Reset Controller’’ on page 287. The DDR3 PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
10.6.3 DDR3 PLL Input Clock Electrical Data/Timing
Table 10-32 applies to both DDR3A and DDR3B memory interfaces.
Table 10-32 DDR3 PLL DDRCLK(N|P) Timing Requirements
(see Figure 10-28 and Figure 10-22)
No.
DDRCLK[P:N]
1 tc(DDRCLKN)
Cycle time _ DDRCLKN cycle time
1 tc(DDRCLKP)
Cycle time _ DDRCLKP cycle time
3 tw(DDRCLKN)
Pulse width _ DDRCLKN high
2 tw(DDRCLKN)
Pulse width _ DDRCLKN low
2 tw(DDRCLKP)
Pulse width _ DDRCLKP high
3 tw(DDRCLKP)
Pulse width _ DDRCLKP low
4 tr(DDRCLK_200 mV) Transition time _ DDRCLK differential rise time (200 mV)
4 tf(DDRCLK_200 mV) Transition time _ DDRCLK differential fall time (200 mV)
5 tj(DDRCLKN)
Jitter, peak_to_peak _ periodic DDRCLKN
5 tj(DDRCLKP)
End of Table 10-32
Jitter, peak_to_peak _ periodic DDRCLKP
Min
Max Unit
3.2
25 ns
3.2
25 ns
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
50
350 ps
50
350 ps
0.02*tc(DDRCLKN) ps
0.02*tc(DDRCLKP) ps
Figure 10-28 DDR3 PLL DDRCLK Timing
DDRCLKN
DDRCLKP
1
2
3
4
5
10.7 PASS PLL
The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select
the input source of the PASS PLL as either the output of the Main PLL mux or the PASSCLK clock reference source.
When coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be programmed to a valid
frequency before being enabled and used.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 311