TCI6636K2H Datasheet, PDF (215/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-7
SPI Device Configuration Field Descriptions
Bit
Field
Description
16
Width
SPI address width configuration
0 = 16-bit address values are used
1 = 24-bit address values are used (default)
15-14 Csel
The chip select field value 0-3(default = 0)
13-12 Mode
Clk Polarity/ Phase
0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input
data is latched on the rising edge of SPICLK.
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge (default).
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input
data is latched on the falling edge of SPICLK.
11-9 Param Idx/Offset
Parameter Table Index: 0-7
This value specifies the parameter table index when the C66x is the boot master
This value specifies the start read address at 8K times this value when the ARM is the boot master
8
Boot Master
Boot Master select
0 = ARM is boot master (default)
1 = C66x is boot master
7
Npin
Selected Chip Select driven
0 = CS0 to the selected chip select is driven
1 = CS0-CS4 to the selected chip select are driven (default)
6-5
Port
Specify SPI port
0 = SPI0 used (default)
1 = SPI1 used
2 = SPI2 used
3 = Reserved
4
Min
Minimum boot configuration select bit.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1
Boot Devices
Boot Devices[3:1]
010 = SPI boot mode
Others = Other boot modes
0
Lendian
End of Table 8-7
Endianess
0 = Big endian
1 = Little endian
8.1.2.2.4 EMIF Boot Device Configuration
Figure 8-6 EMIF Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15
14
13
12
11 10 9
8
765
0
Base Addr
Wait
Width X
Chip Sel
Boot Master=1
Sys PLL Cfg
0
Base Addr
Wait Width
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
4321
0
011
0
011
0
Lendian
Lendian
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
Device Boot and Configuration 215