TCI6636K2H Datasheet, PDF (229/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-24 UART Boot Parameter Table (Part 2 of 2)
Byte Offset Name
36
nDatabits
38
Parity
40
nStopBitsx2
42
Over sample factor
44
Flow Control
46
Data Rate MSW
48
Data Rate LSW
End of Table 8-24
Description
Number of bits supported for data. Only 8 bits is supported.
Bits 01 - 00 Parity
00 = No Parity
01 = Odd parity
10 = Even Parity
Bits 15 - 02 Reserved
Number of stop bits times two. Valid values are 2 (stop bits = 1), 3 (Stop Bits =
1.5), 4 (Stop Bits = 2)
The over sample factor. Only 13 and 16 are valid.
Bits 00 Flow Control
0 = No Flow Control
1 = RTS_CTS flow control
Bits 15 - 01 Reserved
Baud Rate, MSW
Baud Rate, LSW
Configured Through Boot
Configuration Pins
NO
NO
NO
NO
NO
NO
NO
8.1.2.4.9 NAND Boot Parameter Table
Table 8-25 NAND Boot Parameter Table
Byte Offset Name
22
Options
24
numColumnAddrBytes
26
numRowAddrBytes
28
numofDataBytesperPage_msw
30
numofDataBytesperPage_lsw
32
numPagesperBlock
34
busWidth
36
numSpareBytesperPage
38
csel
Description
Bits 00 Geometry
0 = Geometry is taken from this table
1 = Geometry is queried from NAND device.
Bits 01 Clear NAND
0 = NAND Device is a non clear NAND and requires ECC
1 = NAND is a clear NAND and doesn.t need ECC.
Bits 15 - 02 Reserved
Number of bytes used to specify column address
Number of bytes used to specify row address.
Number of data bytes in each page, MSW
Number of data bytes in each page, LSW
Number of Pages per Block
EMIF bus width. Only 8 or 16 bits is supported.
Number of spare bytes allocated per page.
Chip Select number (valid chip selects are 2-5)
40
First Block
End of Table 8-25
First block for RBL to try to read.
Configured Through Boot
Configuration Pins
NO
NO
NO
NO
NO
NO
NO
NO
YES (If ARM is the boot master only
chip select 2 is supported)
YES
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Device Boot and Configuration 229